测试完成，资源超出

Makefile

@@ -18,6 +18,7 @@ back:
 	cp ./src/main/verilog/oser_rst.v ./generated/back/
 	cp ./src/main/verilog/di16_top.v ./generated/back/
 	cp ./src/main/verilog/do16_top.v ./generated/back/
+	cp ./src/main/verilog/qei_top.v ./generated/back/
 	cp ./src/main/verilog/defineParam.v ./generated/back/
 
 

src/main/scala/backBoard/Qei.scala

@@ -41,7 +41,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
   }
 
   val isMiss = for( i <- 0 until 2 ) yield { encordCur(i) === ~encordNxt(i) } 
-  val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) ===  encordNxt(i) } 
+  // val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) ===  encordNxt(i) } 
   val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) } 
 
 
@@ -61,7 +61,6 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
         when(~is2Phase(i)){ //A Phase only
           when( RegNext( phaseA(i) ) & ~phaseA(i) ){
             when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){
-              counter(i) := counter(i)
               isOverflow(i) := true.B
             } .otherwise{
               counter(i) := counter(i) + 1.U
@@ -74,14 +73,12 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
             when( isSign(i) ) {
               when( invDirect(i) ){
                 when( isSetVal(i) & counter(i) === "h80000000".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) - 1.U
                 }
               } .otherwise{
                 when( isSetVal(i) & counter(i) === "h7FFFFFFF".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) + 1.U
@@ -90,14 +87,12 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
             } .otherwise{
               when( invDirect(i) ){
                 when( isSetVal(i) & counter(i) === 0.U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) - 1.U
                 }
               } .otherwise{
                 when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) + 1.U
@@ -108,14 +103,12 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
             when( isSign(i) ) {
               when( invDirect(i) ){
                 when( isSetVal(i) & counter(i) === "h7FFFFFFF".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) + 1.U
                 }
               } .otherwise{
                 when( isSetVal(i) & counter(i) === "h80000000".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) - 1.U
@@ -124,14 +117,12 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
             } .otherwise{
               when( invDirect(i) ){
                 when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) + 1.U
                 }
               } .otherwise{
                 when( isSetVal(i) & counter(i) === 0.U ){
-                  counter(i) := counter(i)
                   isOverflow(i) := true.B
                 } .otherwise{
                   counter(i) := counter(i) - 1.U
@@ -139,7 +130,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
               }
             }
           } .otherwise{
-            assert( isKeep(i) )
+            // assert( isKeep(i) )
           }
         }
         
@@ -153,7 +144,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
 }        
 
 
-class Qei extends BackBoardSlvLocal with BackBoardSlvQei{
+class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQei{
   val phaseAIO    = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
   val phaseBIO    = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
   val phaseZIO    = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }

src/main/verilog/qei_top.v

@@ -0,0 +1,331 @@
+
+
+module qei_top(
+
+  input clock,
+
+     
+  input  lvds_up_din_p,
+  input  lvds_up_din_n, 
+  output lvds_up_dout_p,
+  output lvds_up_dout_n,  
+           
+  input  lvds_down_din_p,
+  input  lvds_down_din_n,  
+  output lvds_down_dout_p,
+  output lvds_down_dout_n,
+
+  output isOnline,
+  input  isLast,
+
+  input DCIn,
+  output        LED_PR,
+  
+  input         phaseAIO_0,
+  input         phaseAIO_1,
+  input         phaseBIO_0,
+  input         phaseBIO_1,
+  input         phaseZIO_0,
+  input         phaseZIO_1
+
+);
+
+
+
+wire clk_400m;
+wire clk_400m_a;
+wire clk_100m_a;
+wire clk_50m_a;
+wire clk_10m_a;
+
+wire lock_o;
+wire reset_stop;
+wire reset_calib;
+
+reg rst_n;
+reg rstn_d;
+
+wire resetn;
+reg  resetn1=1'b1;
+wire timeout_rst;
+reg timeout_rst_d1;
+reg timeout_rst_d2;
+reg timeout_rst_d3;
+reg timeout_rst_d4;
+reg timeout_rst_d5;
+reg timeout_rst_d6;
+reg timeout_rst_d7;
+reg timeout_rst_d8;
+
+reg [3:0] resetCnt = 4'd0;
+always @( posedge clock ) begin
+  if( resetCnt != 4'd15 ) begin
+    resetCnt <= resetCnt + 4'd1;
+  end
+end
+
+assign resetn = resetCnt == 4'd15;
+
+always@(posedge clock or negedge resetn) begin
+  if(!resetn) begin
+    timeout_rst_d1 <= 0;
+    timeout_rst_d2 <= 0;
+    timeout_rst_d3 <= 0;
+    timeout_rst_d4 <= 0;
+    timeout_rst_d5 <= 0;
+    timeout_rst_d6 <= 0;
+    timeout_rst_d7 <= 0;
+    timeout_rst_d8 <= 0;
+  end
+	else begin
+    timeout_rst_d1 <= timeout_rst;
+    timeout_rst_d2 <= timeout_rst_d1;
+    timeout_rst_d3 <= timeout_rst_d2;
+    timeout_rst_d4 <= timeout_rst_d3;
+    timeout_rst_d5 <= timeout_rst_d4;
+    timeout_rst_d6 <= timeout_rst_d5;
+    timeout_rst_d7 <= timeout_rst_d6;
+    timeout_rst_d8 <= timeout_rst_d7;	
+  end
+end
+
+always @(posedge clock or negedge resetn) begin
+  if(!resetn) begin
+    resetn1 <= 1'b1;
+  end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else begin
+    resetn1 <= 1'b1;
+  end
+end
+
+
+reg [5:0]  delay_io_last=6'b111111;
+reg [15:0] counter0=0;
+reg        clk_en0;
+wire       isLast_temp;
+wire       isLast_temp1;
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b0;
+  end	else if(counter0 == 16'd9999) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b1;
+  end else begin
+    counter0 <= counter0 + 1;
+    clk_en0 <= 1'b0;	 
+  end
+end
+
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    delay_io_last <= 6'b111111;
+  end else if(clk_en0 == 1'b1) begin
+    delay_io_last[5:1] <= delay_io_last[4:0];
+    delay_io_last[0] <= isLast;
+  end
+end
+
+
+assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]};
+assign isLast_temp1 = ~isLast_temp;
+
+Gowin_PLLO Gowin_PLLO(
+  .lock(lock_o), 
+  .clkouta(clk_400m),
+  .clkin(clock)
+);
+
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(lvds_down_dout)
+);
+
+
+TLVDS_IBUF lvds_downstream_in(
+  .O(lvds_down_din),
+  .I(lvds_down_din_p),
+  .IB(lvds_down_din_n)
+);
+
+
+TLVDS_OBUF lvds_upstream_out(
+  .O(lvds_up_dout_p),
+  .OB(lvds_up_dout_n),
+  .I(lvds_up_dout)
+);
+
+
+TLVDS_IBUF lvds_upstream_in(
+  .O(lvds_up_din),
+  .I(lvds_up_din_p),
+  .IB(lvds_up_din_n)
+);
+
+
+DHCEN dhcen_inst2 (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
+);
+
+
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(resetn && resetn1),
+  .pll_lock(lock_o), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_400m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m_a)
+);
+
+
+defparam Inst2_CLKDIVC.DIV_MODE="2";
+defparam Inst2_CLKDIVC.GSREN="false";
+CLKDIV Inst2_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_100m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_50m_a)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE="5";
+defparam Inst5_CLKDIVC.GSREN="false";
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_50m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_10m_a)
+);
+
+wire [7:0] downstream_rx_data_out;
+wire downstream_rx_data_valid;
+wire downstream_rx_crc_valid;
+wire downstream_rx_crc_err;
+wire upstream_tx_data_ready;
+wire [7:0] upstream_tx_data_in;
+
+wire downstream_rx_cdr_err;
+wire upstream_rx_cdr_err;
+
+lvds_bus_slave_top i_lvds_bus_slave(
+  .rst_n(resetn && resetn1),
+  .reset_calib(reset_calib),
+  .oser_pclk(clk_10m_a),
+  .oser_fclk(clk_50m_a),
+  .ides_pclk(clk_100m_a),
+  .ides_fclk(clk_400m_a),
+  .timeout_rst(timeout_rst), //add 240523
+
+  .lvds_down_din(lvds_down_din),
+  .lvds_down_dout(lvds_down_dout),
+  .lvds_up_din(lvds_up_din),
+  .lvds_up_dout(lvds_up_dout),
+    
+  .downstream_rx_data_valid(downstream_rx_data_valid), 
+    .downstream_rx_unicast_pkg_valid(),
+  .downstream_rx_data_out(downstream_rx_data_out),
+  .downstream_rx_crc_valid(downstream_rx_crc_valid),
+  .downstream_rx_crc_err(downstream_rx_crc_err),
+    .downstream_rx_crc_err_counter(),
+  .downstream_rx_cdr_err(downstream_rx_cdr_err),
+    .downstream_sync(),
+  .upstream_tx_data_ready(upstream_tx_data_ready),
+    .upstream_tx_unicast_pkg_ready(),
+  .upstream_tx_data_in(upstream_tx_data_in),
+    .upstream_rx_crc_valid(),
+    .upstream_rx_crc_err(),
+    .upstream_rx_crc_err_counter(),
+  .upstream_rx_cdr_err(upstream_rx_cdr_err),
+
+    .local_slave_id(),
+    .test_downstream_rx_10b_data(),
+    .test_downstream_rx_8b_data(),
+    .test_downstream_rx_state_machine(),
+    .test_downstream_tx_en(),
+    .test_downstream_tx_8b_data(),
+    .test_downstream_tx_10b_data(),
+    .test_upstream_rx_10b_data(),
+    .test_upstream_rx_8b_data(),
+    .test_upstream_rx_state_machine(),
+    .test_upstream_tx_en(),
+    .test_upstream_tx_8b_data(),
+    .test_upstream_tx_10b_data()
+  );
+
+
+
+
+
+
+Qei i_qei(
+  .reset(~resetn),
+  .clock(clk_10m_a),
+
+  .io_isOnline(isOnline),
+  .io_isLast(isLast_temp1),
+  .io_DCIn(DCIn),
+
+  .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
+  .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
+  .io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid),
+  .io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err),
+  .io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready),
+  .io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in),
+  .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
+  .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err),
+
+  .param_vendorID(`VENDORID),
+  .param_moduleID(`MODULEID),
+  .param_hwVersion(`HWVERSION),
+  .param_swVersion(`SWVERSION),
+  .param_serial(`SERIAL),
+
+  .LED_PR(LED_PR),
+
+  .phaseAIO_0(phaseAIO_0),
+  .phaseAIO_1(phaseAIO_1),
+  .phaseBIO_0(phaseBIO_0),
+  .phaseBIO_1(phaseBIO_1),
+  .phaseZIO_0(phaseZIO_0),
+  .phaseZIO_1(phaseZIO_1)
+);
+
+
+
+
+
+endmodule
+
+
+
+