测试完成,资源超出
This commit is contained in:
1
Makefile
1
Makefile
@@ -18,6 +18,7 @@ back:
|
||||
cp ./src/main/verilog/oser_rst.v ./generated/back/
|
||||
cp ./src/main/verilog/di16_top.v ./generated/back/
|
||||
cp ./src/main/verilog/do16_top.v ./generated/back/
|
||||
cp ./src/main/verilog/qei_top.v ./generated/back/
|
||||
cp ./src/main/verilog/defineParam.v ./generated/back/
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user