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修复错误位宽，加入islast

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This commit is contained in:
Ruige Lee (WSL)
2025-01-17 16:21:46 +08:00
parent bf0e345cc9
commit 33f2160365
6 changed files with 53 additions and 32 deletions
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2
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -46,7 +46,7 @@ trait CDRInOverSample{ this: CDRInBase =>
// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } ) // Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) } val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) )
val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
when( sampleReg(0) ^ sampleReg(1) ){ when( sampleReg(0) ^ sampleReg(1) ){
arbLock := arbCnt arbLock := arbCnt

36
src/main/scala/backBoard/ebus/TL2CDR.scala
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@@ -69,20 +69,20 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
val rxFifo = Module(new Queue(UInt(32.W), 16)) val rxFifo = Module(new Queue(UInt(32.W), 16))
// val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) ) // val isTLWriteSoftReset = io.mem.fire & io.mem.addr(5,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
} }
trait TL2CDRTx{ this: TL2CDRBase => trait TL2CDRTx{ this: TL2CDRBase =>
// val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U ) // val isTLReadStatus = io.mem.fire & io.mem.addr(5,0) === "h0".U & ( io.mem.wstrb === 0.U )
// val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U ) // val isTLWriteTxLen = io.mem.fire & io.mem.addr(5,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
// val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U ) // val isTLWriteTxFifo = io.mem.fire & io.mem.addr(5,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) val isTLReadStatus = io.tla.fire & io.tla.bits.address(5,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(5,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(5,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val txLen = RegInit(0.U(12.W)) val txLen = RegInit(0.U(12.W))
@@ -161,13 +161,13 @@ trait TL2CDRTx{ this: TL2CDRBase =>
trait TL2CDRRx{ this: TL2CDRBase => trait TL2CDRRx{ this: TL2CDRBase =>
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U ) // val isTLReadRxStatus = io.mem.fire & io.mem.addr(5,0) === "h14".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U ) // val isTLReadRxLen = io.mem.fire & io.mem.addr(5,0) === "h18".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U ) // val isTLReadRxFifo = io.mem.fire & io.mem.addr(5,0) === "h1c".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) // val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(5,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxLen = io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(12.W)) val rxLen = RegInit(0.U(12.W))
@@ -241,8 +241,8 @@ with TL2CDRTx with TL2CDRRx
with TL2CDRIsLast with TL2CDRIsLast
{ {
// val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U // val isWriteTransDir = io.mem.fire & io.mem.addr(5,0) === "hc".U & io.mem.wstrb =/= 0.U
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isWriteTransDir = io.tla.fire & io.tla.bits.address(5,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle)) val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W)) val rdata = Reg(UInt(32.W))
@@ -258,9 +258,9 @@ with TL2CDRIsLast
// io.mem.ready := // io.mem.ready :=
// ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | // ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) ) // ( io.mem.wstrb === 0.U & Mux( io.mem.addr(5,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid io.tld.valid := tlDValid
io.interrupt(0) := intTxEnd io.interrupt(0) := intTxEnd

2
src/main/scala/backBoard/ebus/b4b5.scala
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@@ -60,6 +60,6 @@ object Dualb4b5Encoder{
object Dualb4b5Decoder{ object Dualb4b5Decoder{
def apply( enq: UInt ): UInt = { def apply( enq: UInt ): UInt = {
require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" ) require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" )
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(5,0)) ) Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
} }
} }

16
tb/sw/src/MstMain.c
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@@ -85,11 +85,21 @@ void main()
*plic_priority_6 = 1; *plic_priority_6 = 1;
*plic_threshold_0 = 0; *plic_threshold_0 = 0;
{//再写一次实现延迟，等从机的复位完成
*plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6;
*plic_priority_3 = 1;
*plic_priority_4 = 1;
*plic_priority_5 = 1;
*plic_priority_6 = 1;
*plic_threshold_0 = 0;
}
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 0;
register uint32_t flag;
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 0;
register uint32_t flag;
// asm volatile ( //timer 2s // asm volatile ( //timer 2s
// "1:\n" // "1:\n"

10
tb/sw/src/SlvMain.c
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@@ -86,7 +86,7 @@ void main()
while(1){ while(1){
*cdr_softReset = 1; //复位脉冲 *cdr_softReset = 1; //复位脉冲
*cdr_direct = 0; *cdr_direct = 0;
isLast = *; isLast = *cdr_IsLast;
// asm volatile( // asm volatile(
// "sw x0, 0x10(x0)\n" //cdr_softReset 写入任意值进行复位//复位脉冲 // "sw x0, 0x10(x0)\n" //cdr_softReset 写入任意值进行复位//复位脉冲
@@ -100,7 +100,7 @@ void main()
// *WriteGpio = 0x01; // *WriteGpio = 0x01;
//等待接收开始中断 //等待接收开始中断
while(!flag_intRxStart) while(!flag_intRxStart);
// asm volatile ( // asm volatile (
// "1:\n" // "1:\n"
// "andi %0, sp, 0x04\n" // "andi %0, sp, 0x04\n"
@@ -134,7 +134,7 @@ void main()
//接收本地包 //接收本地包
for( uint32_t i = 0; i < 2; i++ ) { for( uint32_t i = 0; i < 2; i++ ) {
if( *flag_intRxError ){ if( flag_intRxError ){
while(1); while(1);
} }
*(localData+i) = *cdr_rxFifo; *(localData+i) = *cdr_rxFifo;
@@ -151,13 +151,13 @@ void main()
// *WriteGpio = 0x07; // *WriteGpio = 0x07;
register uint32_t downSendLen; register uint32_t downSendLen;
downSendLen = downRecvLen - 8;
if(!isLast){ if(!isLast){
// 下行转发新建包头 // 下行转发新建包头
register uint32_t downSendHead; register uint32_t downSendHead;
*cdr_txLen = downRecvLen; *cdr_txLen = downRecvLen;
downSendLen = downRecvLen - 8;
downSendHead = (downSendLen << 20) | ( 0 << 16) | 0; downSendHead = (downSendLen << 20) | ( 0 << 16) | 0;
*cdr_txFifo = downSendHead; *cdr_txFifo = downSendHead;
*cdr_txFifo = 0; *cdr_txFifo = 0;
@@ -425,7 +425,7 @@ void main()
// ); // );
slvNum = 64 - ( downRecvLen >> 3 ); slvNum = 64 - ( downRecvLen >> 3 );
*WriteGpio = 1 << slvNum; // *WriteGpio = 1 << slvNum;
} else if ( operator == 1 ){ } else if ( operator == 1 ){
// error(); // error();

19
tb/verilator/SimTop.v
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@@ -81,7 +81,9 @@ ExampleRocketSystem s_rocket_mst(
.cdrio_uDatIn(uDatSer[0]), .cdrio_uDatIn(uDatSer[0]),
.cdrio_uDatOut(), .cdrio_uDatOut(),
.cdrio_dDatIn(1'b0), .cdrio_dDatIn(1'b0),
.cdrio_dDatOut(dDatSer[0]) .cdrio_dDatOut(dDatSer[0]),
.cdrio_isOnline(),
.cdrio_isLast(1'b0)
); );
@@ -138,7 +140,10 @@ ExampleRocketSystem s_rocket_slv0(
.cdrio_uDatIn(uDatSer[1]), .cdrio_uDatIn(uDatSer[1]),
.cdrio_uDatOut(uDatSer[0]), .cdrio_uDatOut(uDatSer[0]),
.cdrio_dDatIn(dDatSer[0]), .cdrio_dDatIn(dDatSer[0]),
.cdrio_dDatOut(dDatSer[1]) .cdrio_dDatOut(dDatSer[1]),
.cdrio_isOnline(),
.cdrio_isLast(1'b0)
); );
@@ -195,7 +200,10 @@ ExampleRocketSystem s_rocket_slv1(
.cdrio_uDatIn(uDatSer[2]), .cdrio_uDatIn(uDatSer[2]),
.cdrio_uDatOut(uDatSer[1]), .cdrio_uDatOut(uDatSer[1]),
.cdrio_dDatIn(dDatSer[1]), .cdrio_dDatIn(dDatSer[1]),
.cdrio_dDatOut(dDatSer[2]) .cdrio_dDatOut(dDatSer[2]),
.cdrio_isOnline(),
.cdrio_isLast(1'b0)
); );
@@ -252,7 +260,10 @@ ExampleRocketSystem s_rocket_slv2(
.cdrio_uDatIn(1'b0), .cdrio_uDatIn(1'b0),
.cdrio_uDatOut(uDatSer[2]), .cdrio_uDatOut(uDatSer[2]),
.cdrio_dDatIn(dDatSer[2]), .cdrio_dDatIn(dDatSer[2]),
.cdrio_dDatOut() .cdrio_dDatOut(),
.cdrio_isOnline(),
.cdrio_isLast(1'b1)
); );