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修复错误位宽，加入islast

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Ruige Lee (WSL)
2025-01-17 16:21:46 +08:00
parent bf0e345cc9
commit 33f2160365
6 changed files with 53 additions and 32 deletions
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36
src/main/scala/backBoard/ebus/TL2CDR.scala
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@@ -69,20 +69,20 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
val rxFifo = Module(new Queue(UInt(32.W), 16))
// val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
// val isTLWriteSoftReset = io.mem.fire & io.mem.addr(5,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
}
trait TL2CDRTx{ this: TL2CDRBase =>
// val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U )
// val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
// val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
// val isTLReadStatus = io.mem.fire & io.mem.addr(5,0) === "h0".U & ( io.mem.wstrb === 0.U )
// val isTLWriteTxLen = io.mem.fire & io.mem.addr(5,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
// val isTLWriteTxFifo = io.mem.fire & io.mem.addr(5,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
val isTLReadStatus = io.tla.fire & io.tla.bits.address(5,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(5,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(5,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val txLen = RegInit(0.U(12.W))
@@ -161,13 +161,13 @@ trait TL2CDRTx{ this: TL2CDRBase =>
trait TL2CDRRx{ this: TL2CDRBase =>
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(5,0) === "h14".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxLen = io.mem.fire & io.mem.addr(5,0) === "h18".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxFifo = io.mem.fire & io.mem.addr(5,0) === "h1c".U & ( io.mem.wstrb === 0.U )
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(5,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(12.W))
@@ -241,8 +241,8 @@ with TL2CDRTx with TL2CDRRx
with TL2CDRIsLast
{
// val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
// val isWriteTransDir = io.mem.fire & io.mem.addr(5,0) === "hc".U & io.mem.wstrb =/= 0.U
val isWriteTransDir = io.tla.fire & io.tla.bits.address(5,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W))
@@ -258,9 +258,9 @@ with TL2CDRIsLast
// io.mem.ready :=
// ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(5,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid
io.interrupt(0) := intTxEnd