修复错误位宽，加入islast

2025-01-17 16:21:46 +08:00
parent bf0e345cc9
commit 33f2160365
6 changed files with 53 additions and 32 deletions
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -46,7 +46,7 @@ trait CDRInOverSample{ this: CDRInBase =>
  //   Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )

  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
-  arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) )
+  arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) )
  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
  when( sampleReg(0) ^ sampleReg(1) ){
    arbLock := arbCnt