在指导下,修改了仿真程序clock的占空比,仿真成功

2025-02-05 11:10:45 +08:00
parent e9f0653de5
commit 33184f448f
1 changed files with 1 additions and 1 deletions
--- a/tb/verilator/sim_main.cpp
+++ b/tb/verilator/sim_main.cpp
@@ -167,7 +167,7 @@ static void init_and_clock(){
 	//main clock
 	if ( main_time % 40 == 1 ) {
 		top->clock = 1;
-	} else if ( main_time % 40 == 26 ) {
+	} else if ( main_time % 40 == 21 ) {
 		top->clock = 0;
 		main_cycle ++;
 	}