diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 2abc0dc..45ca2fb 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -144,7 +144,8 @@ class SlaveRegisterBundle extends Bundle{ val slvDeltaTime = UInt(32.W) //从站时间戳差值 val deltaFinal = UInt(64.W) //当前时间戳与主站时间差 - + val lvdsWriteAble = UInt(16.W) + def isLVDSWriteAble = lvdsWriteAble(15,8) === "h58".U & lvdsWriteAble.extract(0) } @@ -268,6 +269,7 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ Seq( + (addr === "h18".U ) -> sReg.lvdsWriteAble.extract(0), (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h22".U & isMstMode) -> mReg.isRecCRCErr, //(addr === "h21".U & isMstMode) -> mReg.txLength, @@ -753,34 +755,35 @@ trait InterfaceCheckSM{ this: InterfaceBase => io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U) } -trait InterfaceLVDSop{ this: InterfaceBase => +trait InterfaceEBMMU{ this: InterfaceBase => io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR) + ( 0 until 16 ).map{ i => sReg.ebmmu(i).lAddr := Cat( - RegEnable( io.lvds.dataw(5,0), 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).pAddr := Cat( - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).length := Cat( - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).op := - RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + RegEnable( io.lvds.dataw, 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) sReg.ebmmu(i).isEnable := - RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) + RegEnable( io.lvds.dataw.extract(0), false.B, sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) } } @@ -1121,7 +1124,21 @@ trait InterfaceSystem{ this: InterfaceBase => RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U ) ) + val lvdsWriteAble = RegInit(0.U(16.W)); sReg.lvdsWriteAble := lvdsWriteAble + when( io.lvds.isEnW & (io.lvds.addrw === "h19".U(16.W)) ){ + lvdsWriteAble := Cat( io.lvds.dataw, lvdsWriteAble(7,0) ) + } .elsewhen( isEnW & (addrw === "h19".U(16.W)) ){ + lvdsWriteAble := Cat( dataw, lvdsWriteAble(7,0) ) + } .elsewhen( io.lvds.isEnW & (io.lvds.addrw === "h18".U(16.W)) ){ + lvdsWriteAble := Cat( lvdsWriteAble(15,8), io.lvds.dataw ) + } .elsewhen( isEnW & (addrw === "h18".U(16.W)) ){ + lvdsWriteAble := Cat( lvdsWriteAble(15,8), dataw ) + } + +} + +trait InterfaceInterrupt{ this: InterfaceBase => cReg.intEnable := Cat( 1.U(1.W), //复位中断，时钟为1 //31 上电复位 @@ -1267,11 +1284,8 @@ trait InterfaceSystem{ this: InterfaceBase => } io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse) - - } - trait InterfaceEvent{ this: InterfaceBase => val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) )) @@ -1498,11 +1512,12 @@ trait InterfaceStat{ this: InterfaceBase => class Interface extends InterfaceBase with InterfaceMCUop with InterfaceCheckSM -with InterfaceLVDSop +with InterfaceEBMMU with InterfaceSync with InterfaceStat with InterfaceWdt with InterfaceSystem +with InterfaceInterrupt with InterfaceEvent with InterfaceAnalog { @@ -1521,9 +1536,6 @@ with InterfaceAnalog sReg.localDevIndex := io.localDevIndex - // sReg.isDevOnLeft := io.isDevOnLeft - // sReg.isDevOnLeftModify := io.isDevOnLeftModify - // sReg.indexOfLeftDev := io.indexOfLeftDev sReg.isDevOnRight := io.isDevOnRight sReg.isDevOnRightModify := io.isDevOnRightModify sReg.indexOfRightDev := io.indexOfRightDev