From 3277e76e1911faa0ac1aac2474f5e511f87a1616 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 17 Apr 2025 15:16:42 +0800 Subject: [PATCH] =?UTF-8?q?=E6=8E=A5=E6=94=B6SRAM=E6=8C=87=E5=90=91SM?= =?UTF-8?q?=E5=8D=95=E5=85=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 108 +++++++++++------- 1 file changed, 66 insertions(+), 42 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 672ec26..3493a33 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -20,13 +20,13 @@ class SubMsgHeader extends Bundle{ -class ShareSRAMIO extends Bundle{ - val addr = Input(UInt(15.W)) - val dataw = Input( UInt(8.W) ) - val datar = Output( UInt(8.W) ) - val enw = Input(Bool()) - val enr = Input(Bool()) -} +// class ShareSRAMIO extends Bundle{ +// val addr = Input(UInt(15.W)) +// val dataw = Input( UInt(8.W) ) +// val datar = Output( UInt(8.W) ) +// val enw = Input(Bool()) +// val enr = Input(Bool()) +// } @@ -37,13 +37,18 @@ class SlaveParserIO extends Bundle{ val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) val upOut = Decoupled(new AXIS_Bundle(8)) - val sram_r = Flipped(new ShareSRAMIO) - val sram_w = Flipped(new ShareSRAMIO) + // val sram_r = Flipped(new ShareSRAMIO) + // val sram_w = Flipped(new ShareSRAMIO) + + val dSMenq = Vec(4, Decoupled(UInt(8.W))) + val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W)))) } abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) + + val FRAME_STYLE_COMMON = 0.U val FRAME_STYLE_PROBE = 1.U @@ -228,34 +233,46 @@ abstract class SlaveParserBase extends Module{ downRecParser.io.data.ready := downRecFifo(1).io.enq.ready } - //写入sram + //写入SM val addrw = Reg(UInt(15.W)) when( downRecParser.io.subMsgReq.fire ){ when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ addrw := downRecParser.io.subMsgReq.bits.address - } .otherwise{ - addrw := 0.U //清零方便调试识别 } - } .elsewhen( io.sram_w.enw ){ - addrw := addrw + 1.U } - - io.sram_w.enr := false.B - - io.sram_w.enw := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 + val isWriteSM := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 ( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) | ( isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U)) ) - io.sram_w.addr := addrw - io.sram_w.dataw := downRecParser.io.data.bits + io.dSMenq(0).valid := isWriteSM & addrw === 0.U + io.dSMenq(0).bits := downRecParser.io.data.bits + when( io.dSMenq(0).valid & ~io.dSMenq(0).ready ){ + printf("An Error occur at dSMenq0!\n") + } + io.dSMenq(1).valid := isWriteSM & addrw === 1.U + io.dSMenq(1).bits := downRecParser.io.data.bits + when( io.dSMenq(1).valid & ~io.dSMenq(1).ready ){ + printf("An Error occur at dSMenq1!\n") + } + io.dSMenq(2).valid := isWriteSM & addrw === 2.U + io.dSMenq(2).bits := downRecParser.io.data.bits + when( io.dSMenq(2).valid & ~io.dSMenq(2).ready ){ + printf("An Error occur at dSMenq2!\n") + } + + io.dSMenq(3).valid := isWriteSM & addrw === 3.U + io.dSMenq(3).bits := downRecParser.io.data.bits + when( io.dSMenq(3).valid & ~io.dSMenq(3).ready ){ + printf("An Error occur at dSMenq3!\n") + } @@ -291,11 +308,33 @@ abstract class SlaveParserBase extends Module{ } } + + //读出uSM + + val addrr = Reg(UInt(15.W)) + val readSMAddr := Mux1H(Seq( + ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address, + ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr, + )) + + + + when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + addrr := upRecParser.io.subMsgReq.bits.address + } + + val uSMData = Mux1H(Seq( + (readSMAddr === 0.U) -> io.uSMdeq(0).bits, + (readSMAddr === 1.U) -> io.uSMdeq(1).bits, + (readSMAddr === 2.U) -> io.uSMdeq(2).bits, + (readSMAddr === 3.U) -> io.uSMdeq(3).bits, + )) + when( ~isUpRecPing ){ //req fire 后 已经反相 upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U), - io.sram_r.datar, upRecParser.io.data.bits) + uSMData, upRecParser.io.data.bits) upRecParser.io.data.ready := upRecFifo(0).io.enq.ready upRecFifo(1).io.enq.valid := false.B @@ -307,34 +346,19 @@ abstract class SlaveParserBase extends Module{ upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U), - io.sram_r.datar, upRecParser.io.data.bits) + uSMData, upRecParser.io.data.bits) upRecParser.io.data.ready := upRecFifo(1).io.enq.ready } - //读出SRAM - val addrr = Reg(UInt(15.W)) - when( upRecParser.io.subMsgReq.fire ){ - when(upRecParser.io.subMsgReq.bits.devIndex === localDevIndex){ - addrr := upRecParser.io.subMsgReq.bits.address - } .otherwise{ - addrr := 0.U //用于方便调试 - } - } .elsewhen( io.sram_r.enr ){ - addrr := addrr + 1.U - } - - io.sram_r.enw := false.B - io.sram_r.dataw := 0.U - io.sram_r.enr := - upRecParser.io.stateNext === STATE_PAYLOAD_DATA + io.uSMdeq(0).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 0.U ) + io.uSMdeq(1).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 1.U ) + io.uSMdeq(2).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U ) + io.uSMdeq(3).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U ) + - io.sram_r.addr := Mux1H(Seq( - ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address, - ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr, - )) //子报文下行发送