wrapper

src/main/scala/backBoard/CDR4InBus.scala.bk

@@ -1,118 +0,0 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-import freechips.rocketchip.util._
-
-
-
-
-
-class CDRInBusIO() extends Bundle{
-  val dat = Input(Bool())
-
-
-  val latDat = Decoupled(new CDRData)
-  val flush = Input(Bool())
-}
-
-
-
-class CDRInBus() extends Module{
-  val io: CDRInBusIO = IO(new CDRInBusIO())
-
-  val latValid = RegInit(false.B)
-  val latInfo = RegInit(0.U.asTypeOf(new CDRData))
-  val shiftDat = RegInit(0.U((1+2+ ((new CDRData).getWidth) ).W))
-  val transInfo = shiftDat(1+2+((new CDRData).getWidth)-2,2).asTypeOf(new CDRData)
-
-  val isHashPass = transInfo.isHashPass
-
-
-  when( io.flush ){
-    shiftDat   := 0.U
-    latValid := false.B
-  } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) =/= 1.U ){
-    shiftDat := Cat(shiftDat << 1 , io.dat)
-  } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) === 1.U ){
-    when( transInfo.isHashPass ){
-      latValid := true.B
-      latInfo  := transInfo
-    } .otherwise{
-      shiftDat   := 0.U
-    }
-  }
-
-  io.latDat.valid := latValid
-  io.latDat.bits  := latInfo
-
-}
-
-
-
-
-
-
-
-
-
-
-class CDR4InBusIO extends Bundle{
-  val dat    = Input( Bool() )
-  val refClk = Input( Vec(4, Bool()) )
-
-  val latDat = Decoupled(new CDRData)
-}
-
-class CDR4InBus extends Module{
-  val io: CDR4InBusIO = IO(new CDR4InBusIO)
-
-  val inBusAsync = ( 0 until 4 ).map{ i => Module(new CDRInBus) }
-
-
-  val inBusToAsync = for( i <- 0 until 4 ) yield { Wire( new AsyncBundle(new CDRData) ) }
-  val inBusSyncIO = for( i <- 0 until 4 ) yield {  Wire (new DecoupledIO(new CDRData) ) }
-
-  val inBusMuxValid = RegInit(false.B)
-  val inBusMuxInfo  = RegInit(0.U.asTypeOf(new CDRData))
-
-  io.latDat.valid := inBusMuxValid
-  io.latDat.bits  := inBusMuxInfo
-
-  for( i <- 0 until 4 ){
-    inBusAsync(i).clock    := io.refClk(i).asClock
-    inBusAsync(i).io.dat   := io.dat
-    inBusAsync(i).io.flush := io.latDat.fire
-
-    // inBusToAsync(i) <> ToAsyncBundle( , AsyncQueueParams(sync=2) )
-    inBusSyncIO(i) <> FromAsyncBundle( inBusToAsync(i), 2 )
-
-    withClockAndReset( io.refClk(i).asClock, reset ) {
-      inBusToAsync(i) <> ToAsyncBundle( inBusAsync(i).io.latDat, AsyncQueueParams(sync=2) )
-    }
-    inBusSyncIO(i).ready := false.B
-  }
-
-  when( io.latDat.fire ){
-    inBusMuxValid := false.B
-  } .elsewhen( ~inBusMuxValid ){
-    inBusMuxValid := inBusSyncIO.map{ x => x.valid }.reduce(_|_)
-    inBusMuxInfo  := Mux1H( inBusSyncIO.map{ x => (x.valid -> x.bits) })
-  }
-
-
-
-  ( 0 until 4).map{ i =>
-    ( 0 until i ).map{ j =>
-      assert( Mux(inBusSyncIO(i).valid & inBusSyncIO(j).valid, inBusSyncIO(i).bits.asUInt === inBusSyncIO(j).bits.asUInt, true.B ),
-      "Assert Failed, How can you pass the CRC check?!"  )
-    }
-  }
-
-
-}
-
-
-
-

src/main/scala/backBoard/goWinMst.scala

@@ -0,0 +1,70 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+class CRC_ERR_Bundle extends Bundle{
+  val crc_err       = Bool()
+  val crc_err_count = UInt(8.W)
+  val cdr_err       = Bool()
+}
+
+  class Lvds_Bus_MasterIO extends Bundle{
+    val rst_n     = Input(Bool())
+    val oser_pclk = Input(Bool())
+    val oser_fclk = Input(Bool())
+    val ides_pclk = Input(Bool())
+    val ides_fclk = Input(Bool())
+   
+    val lvds_down_dout = Output(Bool())
+    val lvds_up_din    = Input(Bool())
+     
+    val frame_info_update_en = Input(Bool())
+    val slave_type_num       = Input(UInt(8.W))
+    val slave_data_length    = Input(UInt(8.W))
+    val tx_start             = Input(Bool())
+    val tx_data_in           = Input(UInt(8.W))
+    val tx_data_ready        = Output(Bool())
+    val downstream_busy      = Output(Bool())
+    val rx_data_out          = Output(UInt(8.W))
+    val rx_data_valid        = Output(Bool())
+
+    val upstream_crc = Valid(new CRC_ERR_Bundle)
+
+  }
+
+class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
+
+  val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
+
+  setInline("lvds_bus_master.v",
+              """
+  | lvds_bus_master_top your_instance_name(
+  |   .rst_n(rst_n), //input
+  |   .oser_pclk(oser_pclk), //input 
+  |   .oser_fclk(oser_fclk), //input  
+  |   .ides_pclk(ides_pclk), //input
+  |   .ides_fclk(ides_fclk), //input
+  | 
+  |   .lvds_down_dout(lvds_down_dout), //output
+  |   .lvds_up_din(lvds_up_din), //input
+  |   
+  |   .frame_info_update_en(frame_info_update_en), //input 
+  |   .slave_type_num(slave_type_num), //input [7:0]     
+  |   .slave_data_length(slave_data_length), //input [7:0]
+  |   .tx_start(tx_start), //input   
+  |   .tx_data_in(tx_data_in), //input [7:0]  
+  |   .tx_data_ready(tx_data_ready), //output
+  |   .downstream_busy(downstream_busy), //output 
+  |   .rx_data_out(rx_data_out), //output [7:0]
+  |   .rx_data_valid(rx_data_valid), //output
+  |   .upstream_crc_valid(upstream_crc_valid), //output
+  |   .upstream_crc_err(upstream_crc_err), //output
+  |   .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
+  |   .upstream_cdr_err(upstream_cdr_err) //output 
+  | );
+    """.stripMargin)
+}
+