From 31d2d86f01e394771e0b2b52346ee66ddf27b71b Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sun, 8 Oct 2023 15:54:40 +0800 Subject: [PATCH] =?UTF-8?q?bug:=E9=98=B6=E8=B7=83=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/mac/MacTilelink.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index f066846..e51a401 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -248,6 +248,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val ReadTxDataFromFifo_wb = Wire(Bool()) + val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B) val txfifo_cnt = Wire(UInt(5.W)) val rxfifo_cnt = Wire(UInt(5.W)) @@ -275,7 +276,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - val RxAbortPluse = io.RxAbortSync & RegNext(io.RxAbortSync, false.B)