diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala
index a5600b5..d6c6e48 100644
--- a/src/main/scala/backBoard/ebus/TL2CDR.scala
+++ b/src/main/scala/backBoard/ebus/TL2CDR.scala
@@ -76,7 +76,7 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
 
 
 trait TL2CDRTx{ this: TL2CDRBase =>
-
+  val isTxFifoRelease = Wire(Bool())
   // val isTLReadStatus        = io.mem.fire & io.mem.addr(5,0) === "h0".U & ( io.mem.wstrb === 0.U )
   // val isTLWriteTxLen        = io.mem.fire & io.mem.addr(5,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
   // val isTLWriteTxFifo       = io.mem.fire & io.mem.addr(5,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
@@ -110,7 +110,7 @@ trait TL2CDRTx{ this: TL2CDRBase =>
   }
   
   txFifo.io.deq.ready := 
-    Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
+    isTxFifoRelease & Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
 
   txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
   CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
@@ -259,8 +259,41 @@ trait TL2CDRUserCRC{ this: TL2CDRBase =>
 
 }
 
+trait TL2CDRLimitTimmer{ this: TL2CDRBase =>
+  val intRxStart: Bool
+  val isTLWriteSoftReset: Bool
+  val isTLWriteLimitTimerAim = io.tla.fire & io.tla.bits.address(5,0) === "h2c".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
 
 
+  val limitTimerCnt = RegInit(0.U(16.W))
+  val limitTimerAim = RegInit(0.U(16.W))
+
+  val isLimitTimerTrigger = RegInit(false.B)
+
+  when( isTLWriteSoftReset ){
+    limitTimerCnt := 0.U
+  } .elsewhen( limitTimerCnt =/= limitTimerAim ){
+    when( isLimitTimerTrigger ){
+      limitTimerCnt := limitTimerCnt + 1.U
+    }
+  }
+
+  when( isTLWriteLimitTimerAim ){
+    limitTimerAim := io.tla.bits.data
+  }
+
+  when( isTLWriteSoftReset ){
+    isLimitTimerTrigger := false.B
+  } .elsewhen( intRxStart ){
+    isLimitTimerTrigger := true.B
+  }
+
+  val isTxFifoRelease: Bool
+  isTxFifoRelease := limitTimerCnt === limitTimerAim
+
+
+}
+
 
 
 
@@ -272,6 +305,7 @@ class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
 with TL2CDRTx with TL2CDRRx
 with TL2CDRIsLast
 with TL2CDRUserCRC
+with TL2CDRLimitTimmer
 {
 
   // val isWriteTransDir       = io.mem.fire & io.mem.addr(5,0) === "hc".U & io.mem.wstrb =/= 0.U
@@ -340,7 +374,7 @@ with TL2CDRUserCRC
   } .elsewhen(isTLReadRxCrc){
     rdata := rxCrc.io.crc
   }
-  
+
 }
 
 
diff --git a/tb/sw/tl2cdr/tl2cdr.h b/tb/sw/tl2cdr/tl2cdr.h
index 5d90aa6..61c1959 100644
--- a/tb/sw/tl2cdr/tl2cdr.h
+++ b/tb/sw/tl2cdr/tl2cdr.h
@@ -25,6 +25,7 @@
 #define CDR_ReadIsLast     0x20
 #define CDR_ReadTxCrc      0x24
 #define CDR_ReadRxCrc      0x28
+#define CDR_WriteLimitTimer 0x2c
 
 #define CDR_INT_TXEND   14
 #define CDR_INT_RXERROR 15