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RuigeLee
2023-11-14 17:03:19 +08:00
parent b6767e5187
commit 31213302aa
5 changed files with 184 additions and 30 deletions
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50
src/test/scala/gcd/Mac_test_top.scala
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@@ -1,41 +1,41 @@
package MAC
// package MAC
import chisel3._
import chisel3.util._
// import chisel3._
// import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
// import org.chipsalliance.cde.config._
// import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.tilelink._
// import freechips.rocketchip.interrupts._
class MacTest(implicit p: Parameters) extends Mac{
// class MacTest(implicit p: Parameters) extends Mac{
val tlClientIONode =
TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "tlSlvIO",
sourceId = IdRange(0, 1),
))
)))
// val tlClientIONode =
// TLClientNode(Seq(TLMasterPortParameters.v1(
// Seq(TLMasterParameters.v1(
// name = "tlSlvIO",
// sourceId = IdRange(0, 1),
// ))
// )))
ethReg.configNode := tlClientIONode
// ethReg.configNode := tlClientIONode
val intSinkNode = IntSinkNode(IntSinkPortSimple())
intSinkNode := ethReg.int_node
// val intSinkNode = IntSinkNode(IntSinkPortSimple())
// intSinkNode := ethReg.int_node
val tlSlv = InModuleBody {
tlClientIONode.makeIOs()
}
// val tlSlv = InModuleBody {
// tlClientIONode.makeIOs()
// }
val int = InModuleBody {
intSinkNode.makeIOs()
}
// val int = InModuleBody {
// intSinkNode.makeIOs()
// }
}
// }