尝试流片顶层

2023-11-14 17:03:19 +08:00
parent b6767e5187
commit 31213302aa
5 changed files with 184 additions and 30 deletions
--- a/3
+++ b/3
@@ -11,7 +11,8 @@ compile:
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
 # 	sbt "test:runMain test.testModule"
 	
-
+ef: 
+	sbt "test:runMain test.testModule"

 VSimTop: 
 	rm -rf ./tb/build/