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Merge branch 'dev/qspi' into feature/ShinTop

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This commit is contained in:
Ruige Lee
2025-05-14 16:27:25 +08:00
parent fb8bc91947 ed9bf22016
commit 30df59220f
4 changed files with 249 additions and 216 deletions
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81
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -9,7 +9,7 @@ class CommonRegisterBundle extends Bundle{
val hwSerial = UInt(48.W) val hwSerial = UInt(48.W)
val busRate = UInt(16.W) val busRate = UInt(16.W)
// val spiSel = UInt(2.W) val spiSel = UInt(2.W)
// val isSoftReset = Bool() // val isSoftReset = Bool()
val encryptKey = UInt(128.W) val encryptKey = UInt(128.W)
@@ -93,7 +93,9 @@ class SlaveRegisterBundle extends Bundle{
class InterfaceIO extends Bundle{ class InterfaceIO extends Bundle{
val ospi = new SPIInterfaceIO val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val iqspi = new QSPIInterfaceIO
@@ -123,8 +125,13 @@ class InterfaceIO extends Bundle{
abstract class InterfaceBase extends Module{ abstract class InterfaceBase extends Module{
val io: InterfaceIO = IO(new InterfaceIO) val io: InterfaceIO = IO(new InterfaceIO)
val oSpi = Module(new SpiInterface) val oSpi = Module(new SSpiInterface)
io.ospi <> oSpi.io.spi val oQSpi = Module(new QSpiInterface)
val iQSpi = Module(new QSpiInterface)
io.ospi <> oSpi.spi
io.oqspi <> oQSpi.qspi
io.iqspi <> iQSpi.qspi
val cReg = Wire(new CommonRegisterBundle) val cReg = Wire(new CommonRegisterBundle)
val mReg = Wire(new MasterRegisterBundle) val mReg = Wire(new MasterRegisterBundle)
@@ -152,6 +159,7 @@ abstract class InterfaceBase extends Module{
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h21".U & isMstMode) -> mReg.txLength, (addr === "h21".U & isMstMode) -> mReg.txLength,
(addr === "h27".U ) -> cReg.spiSel
) ++ ) ++
@@ -179,24 +187,57 @@ trait InterfaceMCUop{ this: InterfaceBase =>
oSpi.io.datar :=
MuxCase( 0.U, Array(
((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar, val isEnW = Mux1H(Seq(
((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U, ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar, ( cReg.spiSel === 1.U ) -> oSpi.io.isEnW,
((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U, ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
)) ))
val addrSel = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.addrSel,
( cReg.spiSel === 1.U ) -> oSpi.io.addrSel,
( cReg.spiSel === 2.U ) -> oQSpi.io.addrSel,
))
val dataw = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
( cReg.spiSel === 1.U ) -> oSpi.io.dataw,
( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
))
val isEnR = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnR,
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
))
val datar = MuxCase( 0.U, Array(
((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
((addrSel & "hFF00".U) === "h2000".U) -> 0.U,
((addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
((addrSel & "hFF00".U) === "h3000".U) -> 0.U,
((addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
((addrSel & "hFF00".U) === "h4000".U) -> 0.U,
))
iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
when( isEnW ){
printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrSel)
}
when( isEnR ){
printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrSel)
}
val isEnW = oSpi.io.isEnW
val addrSel = oSpi.io.addrSel
val dataw = oSpi.io.dataw
val isEnR = oSpi.io.isEnR
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U ) cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U )
cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U ) cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U )
@@ -221,6 +262,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}.reverse }.reverse
) )
cReg.spiSel :=
RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h27".U & cReg.mstOrSlv === 0.U )
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U ) mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )

7
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -25,7 +25,9 @@ class ShinTopIO extends Bundle{
val ospi = new SPIInterfaceIO val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
// val req = Flipped(Valid(new Bundle{ // val req = Flipped(Valid(new Bundle{
@@ -74,7 +76,8 @@ abstract class ShinTopBase extends Module{
} }
io.ospi <> interface.io.ospi io.ospi <> interface.io.ospi
io.iqspi <> interface.io.iqspi
io.oqspi <> interface.io.oqspi
val sram = Seq( val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },

157
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -3,7 +3,16 @@ package BACK
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
class SPIInterfaceIO extends Bundle{ class QSPIInterfaceIO extends Bundle{
val sck = Input(Bool())
val mosi = Input(UInt(4.W))
val miso = Output(UInt(4.W))
val isDirIn = Output(Bool())
val csn = Input(Bool())
}
class SSPIInterfaceIO extends Bundle{
val sck = Input(Bool()) val sck = Input(Bool())
val mosi = Input(Bool()) val mosi = Input(Bool())
val miso = Output(Bool()) val miso = Output(Bool())
@@ -11,10 +20,8 @@ class SPIInterfaceIO extends Bundle{
} }
class SpiInterface extends Module{ abstract class SpiInterfaceBase extends Module{
val io = IO(new Bundle{ val io = IO(new Bundle{
val spi = new SPIInterfaceIO
val addrSel = Output(UInt(16.W)) val addrSel = Output(UInt(16.W))
val dataw = Output( UInt(8.W) ) val dataw = Output( UInt(8.W) )
val datar = Input( UInt(8.W) ) val datar = Input( UInt(8.W) )
@@ -22,26 +29,14 @@ class SpiInterface extends Module{
val isEnR = Output(Bool()) val isEnR = Output(Bool())
}) })
val sck = Wire(Bool())
val sck = io.spi.sck val csn = Wire(Bool())
val mosi = io.spi.mosi
val csn = io.spi.csn
// val spiRegDown = Module(new SpiSRAMDown)
// val spiRegUp = Module(new SpiSRAMUp)
// spiRegDown.io.clockr := clk100M
// spiRegDown.io.clockw := clock.asBool
// spiRegUp.io.clockr := clock.asBool
// spiRegUp.io.clockw := clk100M
//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B) val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B) val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
val shiftMOSI = ShiftRegisters(mosi, 3)
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1) val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
@@ -50,7 +45,7 @@ class SpiInterface extends Module{
val exReg = Reg(UInt(8.W)) val exReg = Reg(UInt(8.W))
io.spi.miso := exReg.extract(exReg.getWidth-1)
val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel
val spiCmd = Reg(UInt(8.W)) val spiCmd = Reg(UInt(8.W))
@@ -62,36 +57,28 @@ class SpiInterface extends Module{
val byteSel = Reg(UInt(12.W)) val byteSel = Reg(UInt(12.W))
// spiRegDown.io.addrr := Cat(pageSel, byteSel) io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U
// spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0) io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
// spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
// spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) }
// spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiRead & byteSel >= 3.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiWrite & byteSel >= 3.U
io.dataw := exReg io.dataw := exReg
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
byteSel := 0.U byteSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
bitSel := bitSel + 1.U when( bitSel.andR ){
when( bitSel === 7.U ){
byteSel := byteSel + 1.U byteSel := byteSel + 1.U
} }
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U addrSel := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg addrSel := exReg
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0)) addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U } .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel === 7.U ){ when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrSel := addrSel + 1.U addrSel := addrSel + 1.U
} }
} }
@@ -99,14 +86,35 @@ class SpiInterface extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U spiCmd := "hFF".U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 7.U ){ //CS为低，且SCK上跳的第0byte } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exReg spiCmd := exReg
} }
}
class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO)
sck := spi.sck
csn := spi.csn
spi.miso := exReg.extract(7)
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
bitSel := bitSel + 1.U
}
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 7.U ){ //CS为低，且SCK上跳补一拍 的第0bit } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U exReg := 0.U
} .otherwise{ } .otherwise{
when( isSpiWrite ){ when( isSpiWrite ){
@@ -121,40 +129,43 @@ class SpiInterface extends Module{
exReg := Cat( exReg(6 ,0), shiftMOSI(1) ) exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
} }
}
class QSpiInterface extends SpiInterfaceBase{
val qspi = IO(new QSPIInterfaceIO)
sck := qspi.sck
csn := qspi.csn
qspi.miso := exReg(7, 4)
qspi.isDirIn := isSpiWrite
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
bitSel := ~bitSel
}
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .otherwise{
assert(false.B, "Assert Failed, empty CMD!\n")
}
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(3,0), shiftMOSI(1) )
}
} }
// val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
// when( isCrcPass ){
// localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
// } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){
// localUpdate := localUpdate & ~exMask_100M
// }
// spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U)
// spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
// spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
// spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready
// spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U )
// io.lvdsSlv.upstream_tx_data_in :=
// Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
// val int = RegInit(false.B); interrupt := int
// when( int ){
// int := false.B
// } .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
// int := true.B
// }

210
tb/shinTest/ShinTopSpiTb.v
View File

@@ -15,7 +15,11 @@ module ShinTopSpiTb(
wire spi_sck; wire spi_sck;
wire spi_mosi; wire spi_mosi;
wire spi_miso; wire spi_miso;
reg [4:0] spi_csn; reg [14:0] spi_csn;
wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire isResp; wire isResp;
@@ -29,10 +33,23 @@ ShinTop s_ShinTop_Mst(
.io_uDatIn(uDat_w[0]), .io_uDatIn(uDat_w[0]),
.io_uDatOut(), .io_uDatOut(),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[0]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[0]), .io_ospi_csn (spi_csn[5]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[10]),
.io_rsp_valid(isResp), .io_rsp_valid(isResp),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -49,10 +66,22 @@ ShinTop s_ShinTop_slv0(
.io_uDatIn(uDat_w[1]), .io_uDatIn(uDat_w[1]),
.io_uDatOut(uDat_w[0]), .io_uDatOut(uDat_w[0]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[1]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[1]), .io_ospi_csn (spi_csn[6]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[11]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -69,10 +98,22 @@ ShinTop s_ShinTop_slv1(
.io_uDatIn(uDat_w[2]), .io_uDatIn(uDat_w[2]),
.io_uDatOut(uDat_w[1]), .io_uDatOut(uDat_w[1]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[2]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[2]), .io_ospi_csn (spi_csn[7]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[12]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -89,10 +130,22 @@ ShinTop s_ShinTop_slv2(
.io_uDatIn(uDat_w[3]), .io_uDatIn(uDat_w[3]),
.io_uDatOut(uDat_w[2]), .io_uDatOut(uDat_w[2]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[3]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[3]), .io_ospi_csn (spi_csn[8]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[13]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -109,10 +162,22 @@ ShinTop s_ShinTop_slv3(
.io_uDatIn(1'b0), .io_uDatIn(1'b0),
.io_uDatOut(uDat_w[3]), .io_uDatOut(uDat_w[3]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[4]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[4]), .io_ospi_csn (spi_csn[9]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[14]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -132,7 +197,7 @@ initial begin
clk8x = 0; clk8x = 0;
reset = 0; reset = 0;
spi_csn = 5'b11111; spi_csn = ~15'b0;
#100 #100
reset <= 1; reset <= 1;
@@ -192,23 +257,17 @@ end
end end
assign spi_sck = sck; assign spi_sck = sck;
assign qspi_sck = sck;
reg [7:0] txBuf[0:2047]; reg [7:0] txBuf[0:2047];
reg [7:0] rxBuf[0:2047]; reg [7:0] rxBuf[0:2047];
reg [7:0] exChangeReg; reg [7:0] exChangeReg;
reg [7:0] exChangeReg0;
reg [7:0] exChangeReg1;
reg [7:0] exChangeReg2;
reg [7:0] exChangeReg3;
reg [7:0] exChangeReg4;
// assign spi_mosi[0] = exChangeReg0[7];
// assign spi_mosi[1] = exChangeReg1[7];
// assign spi_mosi[2] = exChangeReg2[7];
// assign spi_mosi[3] = exChangeReg3[7];
// assign spi_mosi[4] = exChangeReg4[7];
assign spi_mosi = exChangeReg[7]; assign spi_mosi = exChangeReg[7];
assign qspi_mosi = exChangeReg[7:4];
reg isReq = 0; reg isReq = 0;
reg isBusy = 0; reg isBusy = 0;
@@ -226,8 +285,8 @@ always @(posedge clock) begin
isBusy <= #5 1'b1; isBusy <= #5 1'b1;
transCnt <= #5 0; transCnt <= #5 0;
byteCnt <= #5 0; byteCnt <= #5 ~12'b0;
bitCnt <= #5 0; bitCnt <= #5 ~3'b0;
spi_csn[idx] <= #5 1'b0; spi_csn[idx] <= #5 1'b0;
exChangeReg <= txBuf[0]; exChangeReg <= txBuf[0];
@@ -235,124 +294,41 @@ always @(posedge clock) begin
end end
wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10;
wire [11:0] nextByteCnt = byteCnt +1;
always @(posedge sck) begin always @(posedge sck) begin
if( isBusy ) begin if( isBusy ) begin
if( transCnt < length ) begin if( transCnt <= length ) begin
if( isQspi ) begin
bitCnt <= ~bitCnt;
end else begin
bitCnt <= bitCnt + 1; bitCnt <= bitCnt + 1;
end
if( bitCnt == 7 ) begin if( &bitCnt ) begin
byteCnt <= byteCnt +1; byteCnt <= byteCnt +1;
transCnt <= transCnt + 1; transCnt <= transCnt + 1;
rxBuf[byteCnt] <= exChangeReg; rxBuf[byteCnt] <= exChangeReg;
exChangeReg <= txBuf[byteCnt+1]; exChangeReg <= txBuf[nextByteCnt];
end else begin
if( isQspi ) begin
exChangeReg <= {exChangeReg[3:0], qspi_miso};
end else begin end else begin
exChangeReg <= {exChangeReg[6:0], spi_miso}; exChangeReg <= {exChangeReg[6:0], spi_miso};
end end
end
end else begin end else begin
isBusy <= #5 1'b0; isBusy <= #5 1'b0;
spi_csn[idx] <= #5 1'b1; spi_csn[idx] <= #5 1'b1;
end end
end end
end end
// task spi_trans( );
// begin
// #10
// `SCKFRE spi_sck[idx] <= 1'b0;
// if( idx == 0 ) exChangeReg0 <= #5 address[7:0];
// else if( idx == 1 ) exChangeReg1 <= #5 address[7:0];
// else if( idx == 2 ) exChangeReg2 <= #5 address[7:0];
// else if( idx == 3 ) exChangeReg3 <= #5 address[7:0];
// else if( idx == 4 ) exChangeReg4 <= #5 address[7:0];
// `SCKFRE spi_sck[idx] <= 1'b1;
// `SCKFRE spi_sck[idx] <= 1'b0;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 address[15:8];
// else if( idx == 1 ) exChangeReg1 <= #5 address[15:8];
// else if( idx == 2 ) exChangeReg2 <= #5 address[15:8];
// else if( idx == 3 ) exChangeReg3 <= #5 address[15:8];
// else if( idx == 4 ) exChangeReg4 <= #5 address[15:8];
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 cmd;
// else if( idx == 1 ) exChangeReg1 <= #5 cmd;
// else if( idx == 2 ) exChangeReg2 <= #5 cmd;
// else if( idx == 3 ) exChangeReg3 <= #5 cmd;
// else if( idx == 4 ) exChangeReg4 <= #5 cmd;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// while( transCnt < length ) begin
// if( idx == 0 ) exChangeReg0 <= #5 txBuf[transCnt];
// else if( idx == 1 ) exChangeReg1 <= #5 txBuf[transCnt];
// else if( idx == 2 ) exChangeReg2 <= #5 txBuf[transCnt];
// else if( idx == 3 ) exChangeReg3 <= #5 txBuf[transCnt];
// else if( idx == 4 ) exChangeReg4 <= #5 txBuf[transCnt];
// transCnt <= transCnt + 1;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// rxBuf[transCnt] <= #5
// idx == 0 ? exChangeReg0 :
// idx == 1 ? exChangeReg1 :
// idx == 2 ? exChangeReg2 :
// idx == 3 ? exChangeReg3 :
// exChangeReg4;
// end
// spi_csn[idx] <= 1'b1;
// #2400
// spi_csn[idx] <= 1'b1;
// end
// endtask
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx ); task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
begin begin