move tlsram to chisel

src/main/scala/mac/MAC.scala

@@ -11,15 +11,15 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
 
 
-  val tlClientIONode = 
+  // val tlClientIONode = 
-    if(!isTileLink){ None } else {
+  //   if(!isTileLink){ None } else {
-      Some(TLClientNode(Seq(TLMasterPortParameters.v1(
+  //     Some(TLClientNode(Seq(TLMasterPortParameters.v1(
-        Seq(TLMasterParameters.v1(
+  //       Seq(TLMasterParameters.v1(
-          name = "tlSlvIO",
+  //         name = "tlSlvIO",
-          sourceId = IdRange(0, 1),
+  //         sourceId = IdRange(0, 1),
-        ))
+  //       ))
-      ))))
+  //     ))))
-    }
+  //   }
 
   val tlMasterNode = 
     if(!isTileLink){ None } else {
@@ -37,25 +37,25 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
       )
     }
 
-  if( !isTileLink ){} else {
+  // if( !isTileLink ){} else {
-    tlMasterNode.get := tlClientIONode.get
+  //   tlMasterNode.get := tlClientIONode.get
-    val tlSlv = InModuleBody {
+    // val tlSlv = InModuleBody {
-      tlClientIONode.get.makeIOs()
+    //   tlClientIONode.get.makeIOs()
-    }
+    // }
-  }
+  // }
 
 
-  val tlMasterIONode = 
+  // val tlMasterIONode = 
-      TLManagerNode(Seq(TLSlavePortParameters.v1(
+  //     TLManagerNode(Seq(TLSlavePortParameters.v1(
-        managers = Seq(TLSlaveParameters.v1(
+  //       managers = Seq(TLSlaveParameters.v1(
-        address = Seq(AddressSet(0x00000000L, 0xFFFFFFFL)),
+  //       address = Seq(AddressSet(0x00000000L, 0xFFFFFFFL)),
-        regionType = RegionType.UNCACHED,
+  //       regionType = RegionType.UNCACHED,
-        executable = false,
+  //       executable = false,
-        supportsGet         = TransferSizes(32/8, 32*4/8),
+  //       supportsGet         = TransferSizes(32/8, 32*4/8),
-        supportsPutFull     = TransferSizes(32/8, 32*4/8),
+  //       supportsPutFull     = TransferSizes(32/8, 32*4/8),
-        supportsPutPartial  = TransferSizes(32/8, 32*4/8)
+  //       supportsPutPartial  = TransferSizes(32/8, 32*4/8)
-      )),
+  //     )),
-      beatBytes = 32/8)))
+  //     beatBytes = 32/8)))
 
 
 
@@ -66,10 +66,10 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
     ))
   )))
 
-  tlMasterIONode := tlClientNode
+  // tlMasterIONode := tlClientNode
-  val tlmST = InModuleBody {
+  // val tlmST = InModuleBody {
-    tlMasterIONode.makeIOs()
+  //   tlMasterIONode.makeIOs()
-  }
+  // }
 
   lazy val module = new MacImp(this)
 

src/main/scala/mac/MacTilelink.scala

@@ -844,12 +844,12 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn], edgeOut: TLEdgeOut)(impli
   //Latching Rx buffer pointer from buffer descriptor;
   when(RxEn & RxEn_q & RxPointerRead){
     RxPointerMSB := ram_do(31,2)    
-  } .elsewhen(MasterWbRX & io.tlMst.get.D.fire ){
+  } .elsewhen(MasterWbRX & io.tlMst.get.A.fire ){
     RxPointerMSB := RxPointerMSB + 1.U // Word access (always word access. m_wb_sel_o are used for selecting bytes)
   }
 
   //Latching last addresses from buffer descriptor (used as byte-half-word indicator);
-  when(MasterWbRX & io.tlMst.get.D.fire ){// After first write all RxByteSel are active
+  when(MasterWbRX & io.tlMst.get.A.fire ){// After first write all RxByteSel are active
     RxPointerLSB_rst := 0.U
   } .elsewhen(RxEn & RxEn_q & RxPointerRead){
     RxPointerLSB_rst := ram_do(1,0)    
@@ -925,7 +925,7 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn], edgeOut: TLEdgeOut)(impli
 
 
   // Generation of the end-of-frame signal
-  when(ShiftEndedSync3 & MasterWbRX & io.tlMst.get.D.fire & RxBufferAlmostEmpty & ~ShiftEnded){
+  when(ShiftEndedSync3 & MasterWbRX & io.tlMst.get.A.fire & RxBufferAlmostEmpty & ~ShiftEnded){
     ShiftEnded := true.B
   } .elsewhen(RxStatusWrite){
     ShiftEnded := false.B
@@ -1082,7 +1082,7 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn], edgeOut: TLEdgeOut)(impli
     mstABits :=
       edgeOut.Put(
         fromSource = 0.U,
-        toAddress = RxPointerMSB,
+        toAddress = RxPointerMSB << 2,
         lgSize = log2Ceil(32/8).U,
         data = rx_fifo.io.data_out,
         mask = RxByteSel,
@@ -1093,7 +1093,7 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn], edgeOut: TLEdgeOut)(impli
     mstABits :=
       edgeOut.Get(
         fromSource = 0.U,
-        toAddress = TxPointerMSB,
+        toAddress = TxPointerMSB << 2,
         lgSize = log2Ceil(32/8).U,
       )._2
   }
@@ -1125,12 +1125,16 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn], edgeOut: TLEdgeOut)(impli
   when(io.tlMst.get.D.fire & io.tlMst.get.D.bits.opcode === 0.U) { assert( MasterWbRX ) }
 
 
-
+    val tlMstAValid_dbg = RegInit(true.B)
-    io.tlMst.get.A.valid := mstAValid
+    io.tlMst.get.A.valid := mstAValid & tlMstAValid_dbg
     io.tlMst.get.A.bits  := mstABits
 
 
-    io.tlMst.get.D.ready := true.B
+    val tlMstDReady = RegInit(true.B)
+
+    dontTouch(tlMstDReady)
+    dontTouch(tlMstAValid_dbg)
+    io.tlMst.get.D.ready := tlMstDReady
 
 
 

src/test/scala/gcd/Mac_test_top.scala

@@ -0,0 +1,52 @@
+package MAC
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+
+
+
+class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
+
+	val mac = LazyModule( new Mac )
+
+
+	val tlRAM = TLRAM(
+    address    = AddressSet(0x00000000L, 0x001FFFFFL),
+    cacheable  = false,
+    executable = false,
+    atomics    = false,
+    beatBytes  = 4,
+    sramReg = true,
+    devName = None,
+  )
+
+	tlRAM := mac.tlClientNode
+
+  if( !isTileLink ){} else {
+
+		val tlClientIONode = 
+			TLClientNode(Seq(TLMasterPortParameters.v1(
+				Seq(TLMasterParameters.v1(
+					name = "tlSlvIO",
+					sourceId = IdRange(0, 1),
+				))
+			)))
+
+		mac.tlMasterNode.get := tlClientIONode
+
+    val tlSlv = InModuleBody {
+      tlClientIONode.makeIOs()
+    }
+  }
+
+	lazy val module = new LazyModuleImp(this) {
+		val io = IO(new MacIO with MDIO)
+
+		io <> mac.module.io
+	}
+}

src/test/scala/gcd/test.scala

@@ -19,7 +19,7 @@ object testModule extends App {
 
   (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new Mac()(cfg))
+    val soc = LazyModule(new MacTest()(cfg))
     soc.module
   })
   ))