move tlsram to chisel

2023-07-11 00:00:26 +08:00
parent 67f93bb464
commit 3037d31028
4 changed files with 95 additions and 39 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -19,7 +19,7 @@ object testModule extends App {

  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
      ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new Mac()(cfg))
+    val soc = LazyModule(new MacTest()(cfg))
    soc.module
  })
  ))