From 2fb450673f5fb9c9bba4b39266ac1d2f96f49884 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 18 Aug 2025 17:39:32 +0800
Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4=E8=A7=A3=E9=94=81=E6=9D=A1?=
 =?UTF-8?q?=E4=BB=B6=E4=B8=BA10=E4=B8=AA=E8=BF=9E=E7=BB=AD0?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala   | 88 +++++++++------------
 src/main/scala/backBoard/shin/ShinTop.scala |  7 +-
 2 files changed, 38 insertions(+), 57 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index e63b08f..be04b28 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -17,14 +17,7 @@ abstract class CDRInBase extends Module{
 
   val io: CDRInIO = IO(new CDRInIO)
 
-  val STATE_IDLE = 0.U
-  val STATE_HEADER = 1.U
-  val STATE_PAYLOAD = 2.U
-
-  val stateNext = Wire(UInt(2.W))
-  val stateCurr = RegNext( stateNext, STATE_IDLE )
-
-  val syncSerDat = Wire(Bool())
+    val syncSerDat = Wire(Bool())
 }
 
 trait CDRInOverSample{ this: CDRInBase =>
@@ -71,30 +64,30 @@ trait CDRInOverSample{ this: CDRInBase =>
 }
 
 trait CDRInMultiSample{ this: CDRInBase =>
-  val testIO = IO(Output(UInt(10.W)))
   val clkNum: Int = 16
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(8, Bool())))
+  val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
 
-  val sampleReg = Wire(Vec(8, Bool()))
+
+  val sampleReg = Wire(Vec(clkNum, Bool()))
   
-  for( i <- 0 until 8 ) {
+  for( i <- 0 until clkNum ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
 
-  val sampleReg_sync = Wire(Vec(16,Bool()))
+  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
 
 
 
-  for( i <- 0 until 8 ){
+  for( i <- 0 until clkNum ){
     sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
   }
 
-  for( i <- 8 until 16 ){
-    sampleReg_sync(i) := ShiftRegister(sampleReg(i-8), 1)
+  for( i <- clkNum until 2*clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
   }
 
   /*
@@ -109,63 +102,49 @@ trait CDRInMultiSample{ this: CDRInBase =>
   */
 
   val flitReg =
-    for( i <- 1 until 15 ) yield {
+    for( i <- 1 until (2*clkNum)-1 ) yield {
       (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
       (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
       (sampleReg_sync(i+0) & sampleReg_sync(i+1))
     }
 
-
-  val arbLock = Reg(UInt( 8.W ))
+  val clearCnt = Reg(UInt(4.W))
+  val arbLock = Reg(UInt( clkNum.W ))
   val isLock = RegInit(false.B)
 
+  when( sampleReg.reduce(_|_) === false.B ){
+    when( clearCnt =/= 10.U ){
+      clearCnt := clearCnt + 1.U
+    }
+  } .otherwise{
+    clearCnt := 0.U
+  }
+
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
   when( ~isLock ){
-    when( flitReg(0) ^ flitReg(1) ){
-      arbLock := "b1".U(16.W) << 0
-      isLock := true.B
-    } .elsewhen( flitReg(1) ^ flitReg(2) ){
-      arbLock := "b1".U(16.W) << 1
-      isLock := true.B
-    } .elsewhen( flitReg(2) ^ flitReg(3) ){
-      arbLock := "b1".U(16.W) << 2
-      isLock := true.B
-    } .elsewhen( flitReg(3) ^ flitReg(4) ){
-      arbLock := "b1".U(16.W) << 3
-      isLock := true.B
-    } .elsewhen( flitReg(4) ^ flitReg(5) ){
-      arbLock := "b1".U(16.W) << 4
-      isLock := true.B
-    } .elsewhen( flitReg(5) ^ flitReg(6) ){
-      arbLock := "b1".U(16.W) << 5
-      isLock := true.B
-    } .elsewhen( flitReg(6) ^ flitReg(7) ){
-      arbLock := "b1".U(16.W) << 6
-      isLock := true.B
-    } .elsewhen( flitReg(7) ^ flitReg(8) ){
-      arbLock := "b1".U(16.W) << 7
-      isLock := true.B
+    for( i <- 0 until clkNum ){
+      val j = clkNum - i -1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        arbLock := "b1".U(clkNum.W) << j
+        isLock := true.B
+      }
     }
-  } .elsewhen( stateNext === STATE_IDLE & stateCurr === STATE_PAYLOAD ){
+  } .elsewhen( clearCnt === 10.U ){
     isLock := false.B
   }
 
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 0 until 8 } yield {
-        (arbLock === (1.U << i)) -> flitReg(i+4)
+      (for { i <- 0 until clkNum } yield {
+        (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2))
       })
     )
 
 
+  syncSerDat := asyncSerDat
 
-
-  syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
-
-
-  testIO := Cat( syncSerDat, Cat(flitReg), io.serDat )
 }
 
 
@@ -177,6 +156,13 @@ trait CDRInAxis{ this: CDRInBase =>
   val ETH_PRE = "b1100010001".U(10.W)
   val ETH_SFD = "b0110100111".U(10.W)
 
+  val STATE_IDLE = 0.U
+  val STATE_HEADER = 1.U
+  val STATE_PAYLOAD = 2.U
+
+  val stateNext = Wire(UInt(2.W))
+  val stateCurr = RegNext( stateNext, STATE_IDLE )
+
 
 
   val bitCnt = Reg(UInt(4.W))
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 818521f..f50fff0 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(8, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
@@ -37,7 +37,6 @@ class ShinTopIO extends Bundle{
   val xtal    = Output(UInt(12.W))
   val spiSel  = Output(UInt(2.W))
 
-  val testIO = Output(UInt(12.W))
 }
 
 
@@ -76,10 +75,6 @@ abstract class ShinTopBase extends Module{
 
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
 
-  io.testIO := Cat(
-    downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
-  )
-
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt