From 2ecb547bc8554ee6ead874a27382d4ef869c4721 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Mon, 15 Sep 2025 15:31:39 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=88=9D=E7=89=88CDRIn?=
 =?UTF-8?q?=E6=96=B9=E6=A1=88?=
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---
 src/main/scala/backBoard/shin/CDRIn.scala   | 99 +++++++++++++++++++++
 src/main/scala/backBoard/shin/ShinTop.scala |  4 +-
 2 files changed, 101 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/shin/CDRIn.scala b/src/main/scala/backBoard/shin/CDRIn.scala
index 18f3d8d..e2e2598 100644
--- a/src/main/scala/backBoard/shin/CDRIn.scala
+++ b/src/main/scala/backBoard/shin/CDRIn.scala
@@ -282,4 +282,103 @@ class CDRInAxis extends Module with RequireAsyncReset{
 }
 
 
+class CDRInOriSample extends Module with RequireAsyncReset{
+  val io: CDRInSampleIO = IO(new CDRInSampleIO)  
+  val clkNum: Int = 16
+  require( clkNum == 16 )
 
+  //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
+  val multiCLK = IO(Input(Vec(clkNum, Bool())))
+
+
+
+  val sampleReg = Wire(Vec(clkNum, Bool()))
+  
+  for( i <- 0 until clkNum ) {
+    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
+  }
+
+  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
+
+
+
+  for( i <- 0 until clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2, false.B, true.B)
+  }
+
+  for( i <- clkNum until 2*clkNum ){
+    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1, false.B, true.B)
+  }
+
+  val flitReg =
+    for( i <- 1 until (2*clkNum)-1 ) yield {
+      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+    }
+
+  val clearCnt = RegInit(0.U(4.W))
+  val checkCnt = RegInit(0.U(4.W))
+  val arbLock  = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
+  val arbCali  = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
+  val isLock = RegInit(false.B)
+
+  when( sampleReg_sync.reduce(_|_) === false.B ){
+    when( clearCnt =/= 10.U ){
+      clearCnt := clearCnt + 1.U
+    }
+  } .otherwise{
+    clearCnt := 0.U
+  }
+
+  when( ~isLock ){
+    checkCnt := 0.U
+  } .otherwise{
+    checkCnt := checkCnt + 1.U
+  }
+
+  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
+
+  when( ~isLock ){
+    for( i <- 3 until 19 ){
+      val j = 19 - i - 1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        arbLock := j.U
+        arbCali := j.U
+      }
+    }
+  }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
+    for( i <- 0 until 22 ){
+      val j = 22 - i -1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
+          arbCali := arbCali - 1.U
+        } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
+          arbCali := arbCali + 1.U
+        }
+      }
+    }
+  }
+
+  when( ~isLock ){
+    for( i <- 3 until 19 ){
+      val j = 19 - i - 1
+      when( flitReg(j) ^ flitReg(j+1) ){
+        isLock := true.B
+      }
+    }
+  } .elsewhen( clearCnt === 10.U ){
+    isLock := false.B
+  }
+
+
+  val asyncSerDat = 
+    Mux1H(
+      (for { i <- 0 until 22 } yield {
+        (arbCali === i.U) -> flitReg(i+(8))
+      })
+    )
+
+
+  io.syncSerDat := asyncSerDat
+}
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 6281bb6..b9b8409 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -41,8 +41,8 @@ class ShinTop extends Module with RequireAsyncReset{
   }
 
   {
-    val downCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16))
-    val upCDRInSampleC   = Module(new CDRInMultiSample(clkNum = 16))
+    val downCDRInSampleC = Module(new CDRInOriSample)
+    val upCDRInSampleC   = Module(new CDRInOriSample)
 
     downCDRInSampleC.multiCLK := io.multiCLK
     upCDRInSampleC.multiCLK   := io.multiCLK