From 2e19a95b92fc38649df94d0707d88527aa241a91 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 18 Sep 2025 17:55:50 +0800
Subject: [PATCH] =?UTF-8?q?=E5=BB=BA=E7=AB=8B=E5=8F=8C=E8=BE=B9=E6=B2=BF?=
 =?UTF-8?q?=E9=87=87=E6=A0=B7Flip-Flop=E5=BA=95=E5=B1=82=E9=80=BB=E8=BE=91?=
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---
 src/main/scala/util/DDFlipFlop.scala | 74 ++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 src/main/scala/util/DDFlipFlop.scala

diff --git a/src/main/scala/util/DDFlipFlop.scala b/src/main/scala/util/DDFlipFlop.scala
new file mode 100644
index 0000000..0125ac8
--- /dev/null
+++ b/src/main/scala/util/DDFlipFlop.scala
@@ -0,0 +1,74 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class DDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset){
+  private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
+  private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
+
+  val value: T = (pReg.asUInt ^ nReg.asUInt).asTypeOf(init)
+
+  private val next = WireDefault(value)
+
+  def :=(d:T): Unit = { next := d }
+
+  pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init)
+  nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init)
+
+  def apply(): T = value
+
+}
+
+object DDRegInit{
+  def apply[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset): DDRegInit[T] = {
+    new DDRegInit(init, pclk, nclk, reset)
+  }
+
+}
+
+
+class DDRegNext[T<:Data](d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset ){
+  private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
+  private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
+
+  pReg := (d.asUInt ^ nReg.asUInt).asTypeOf(init)
+  nReg := (d.asUInt ^ pReg.asUInt).asTypeOf(init)
+  
+  val value: T = (pReg.asUInt ^ nReg.asUInt).asTypeOf(init)
+  def apply(): T = value
+}
+
+
+object DDRegNext{
+  def apply[T<:Data]( d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset ): DDRegNext[T] = {
+    new DDRegNext(d, init, pclk, nclk, reset )
+  } 
+}
+
+class DDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset ){
+  private val pRegs = withClockAndReset(pclk, reset) { RegInit(VecInit(Seq.fill(n)( init ))) }
+  private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) }
+
+  // 移位逻辑：首位采样输入，其他依次移位
+  pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init)
+  for(i <- 1 until n) {
+    pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)
+  }
+
+  nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
+  for(i <- 1 until n) {
+    nRegs(i) := (nRegs(i-1).asUInt ^ pRegs(i).asUInt).asTypeOf(init)
+  }
+
+  // 输出为 pRegs 与 nRegs 异或
+  def apply(): Seq[T] = (pRegs zip nRegs).map{ case (a, b) => (a.asUInt ^ b.asUInt).asTypeOf(init) }
+}
+
+
+object DDShiftRegisters{
+  def apply[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset ): DDShiftRegisters[T] = {
+    new DDShiftRegisters( in, n, init, en, pclk, nclk, reset )
+  }
+}
+