搭建QSPI
This commit is contained in:
Ruige Lee
@@ -3,7 +3,16 @@ package BACK
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import chisel3._
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import chisel3.util._
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class SPIInterfaceIO extends Bundle{
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class QSPIInterfaceIO extends Bundle{
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val sck = Input(Bool())
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val mosi = Input(UInt(4.W))
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val miso = Output(UInt(4.W))
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val isDirIn = Output(Bool())
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val csn = Input(Bool())
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}
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class SSPIInterfaceIO extends Bundle{
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val sck = Input(Bool())
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val mosi = Input(Bool())
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val miso = Output(Bool())
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@@ -11,10 +20,8 @@ class SPIInterfaceIO extends Bundle{
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}
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class SpiInterface extends Module{
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abstract class SpiInterfaceBase extends Module{
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val io = IO(new Bundle{
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val spi = new SPIInterfaceIO
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val addrSel = Output(UInt(16.W))
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val dataw = Output( UInt(8.W) )
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val datar = Input( UInt(8.W) )
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@@ -22,26 +29,14 @@ class SpiInterface extends Module{
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val isEnR = Output(Bool())
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})
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val sck = io.spi.sck
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val mosi = io.spi.mosi
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val csn = io.spi.csn
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// val spiRegDown = Module(new SpiSRAMDown)
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// val spiRegUp = Module(new SpiSRAMUp)
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// spiRegDown.io.clockr := clk100M
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// spiRegDown.io.clockw := clock.asBool
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// spiRegUp.io.clockr := clock.asBool
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// spiRegUp.io.clockw := clk100M
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val sck = Wire(Bool())
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val csn = Wire(Bool())
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//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
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val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
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val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
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val shiftMOSI = ShiftRegisters(mosi, 3)
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val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
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@@ -50,7 +45,7 @@ class SpiInterface extends Module{
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val exReg = Reg(UInt(8.W))
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io.spi.miso := exReg.extract(exReg.getWidth-1)
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val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel
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val spiCmd = Reg(UInt(8.W))
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@@ -62,36 +57,28 @@ class SpiInterface extends Module{
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val byteSel = Reg(UInt(12.W))
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// spiRegDown.io.addrr := Cat(pageSel, byteSel)
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// spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)
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// spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
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// spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) }
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// spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
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io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiRead & byteSel >= 3.U
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io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & isSpiWrite & byteSel >= 3.U
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io.dataw := exReg
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io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiRead & byteSel >= 3.U
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io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiWrite & byteSel >= 3.U
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io.dataw := exReg
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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byteSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := bitSel + 1.U
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when( bitSel === 7.U ){
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when( bitSel.andR ){
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byteSel := byteSel + 1.U
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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addrSel := 0.U
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} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
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addrSel := exReg
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} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
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addrSel := Cat(exReg, addrSel(7,0))
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} .otherwise{ // byteSel > 1.U
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when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel === 7.U ){
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when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel.andR ){
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addrSel := addrSel + 1.U
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}
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}
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@@ -99,13 +86,34 @@ class SpiInterface extends Module{
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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spiCmd := "hFF".U
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} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 7.U ){ //CS为低，且SCK上跳的第0byte
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} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel.andR ){ //CS为低，且SCK上跳的第0byte
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spiCmd := exReg
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}
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}
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class SSpiInterface extends SpiInterfaceBase{
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val spi = IO(new SSPIInterfaceIO)
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sck := spi.sck
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csn := spi.csn
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spi.miso := exReg.extract(7)
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := bitSel + 1.U
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}
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val shiftMOSI = ShiftRegisters(spi.mosi, 3)
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
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exReg := 0.U
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} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 7.U ){ //CS为低，且SCK上跳补一拍 的第0bit
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} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit
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when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
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exReg := 0.U
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} .otherwise{
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@@ -121,40 +129,43 @@ class SpiInterface extends Module{
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exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
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}
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}
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class QSpiInterface extends SpiInterfaceBase{
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val qspi = IO(new QSPIInterfaceIO)
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sck := qspi.sck
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csn := qspi.csn
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qspi.miso := exReg(7, 4)
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qspi.isDirIn := isSpiWrite
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := ~bitSel
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}
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val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
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exReg := 0.U
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} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit
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when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
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exReg := 0.U
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} .otherwise{
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when( isSpiWrite ){
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exReg := 0.U
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} .elsewhen( isSpiRead ){
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exReg := io.datar
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} .otherwise{
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assert(false.B, "Assert Failed, empty CMD!\n")
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}
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}
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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exReg := Cat( exReg(6 ,4), shiftMOSI(1) )
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}
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}
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// val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
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// when( isCrcPass ){
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// localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
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// } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){
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// localUpdate := localUpdate & ~exMask_100M
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// }
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// spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U)
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// spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
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// spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
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// spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready
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// spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U )
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// io.lvdsSlv.upstream_tx_data_in :=
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// Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
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// val int = RegInit(false.B); interrupt := int
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// when( int ){
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// int := false.B
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// } .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
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// int := true.B
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// }
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