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搭建QSPI

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This commit is contained in:
Ruige Lee
2025-05-13 18:03:22 +08:00
parent fb8bc91947
commit 2e186a8365
3 changed files with 148 additions and 95 deletions
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77
src/main/scala/backBoard/shin/Interface.scala
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@@ -9,7 +9,7 @@ class CommonRegisterBundle extends Bundle{
val hwSerial = UInt(48.W)
val busRate = UInt(16.W)
// val spiSel = UInt(2.W)
val spiSel = UInt(2.W)
// val isSoftReset = Bool()
val encryptKey = UInt(128.W)
@@ -93,7 +93,9 @@ class SlaveRegisterBundle extends Bundle{
class InterfaceIO extends Bundle{
val ospi = new SPIInterfaceIO
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val iqspi = new QSPIInterfaceIO
@@ -123,8 +125,13 @@ class InterfaceIO extends Bundle{
abstract class InterfaceBase extends Module{
val io: InterfaceIO = IO(new InterfaceIO)
val oSpi = Module(new SpiInterface)
io.ospi <> oSpi.io.spi
val oSpi = Module(new SSpiInterface)
val oQSpi = Module(new QSpiInterface)
val iQSpi = Module(new QSpiInterface)
io.ospi <> oSpi.spi
io.oqspi <> oQSpi.qspi
io.iqspi <> iQSpi.qspi
val cReg = Wire(new CommonRegisterBundle)
val mReg = Wire(new MasterRegisterBundle)
@@ -152,6 +159,7 @@ abstract class InterfaceBase extends Module{
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h21".U & isMstMode) -> mReg.txLength,
(addr === "h27".U ) -> cReg.spiSel
) ++
@@ -179,24 +187,53 @@ trait InterfaceMCUop{ this: InterfaceBase =>
oSpi.io.datar :=
MuxCase( 0.U, Array(
((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
val isEnW = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnW,
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
))
val addrSel = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.addrSel,
( cReg.spiSel === 1.U ) -> oSpi.io.addrSel,
( cReg.spiSel === 2.U ) -> oQSpi.io.addrSel,
))
val dataw = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
( cReg.spiSel === 1.U ) -> oSpi.io.dataw,
( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
))
val isEnR = Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnR,
( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
))
val datar = MuxCase( 0.U, Array(
((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
((addrSel & "hFF00".U) === "h2000".U) -> 0.U,
((addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
((addrSel & "hFF00".U) === "h3000".U) -> 0.U,
((addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
((addrSel & "hFF00".U) === "h4000".U) -> 0.U,
))
iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
val isEnW = oSpi.io.isEnW
val addrSel = oSpi.io.addrSel
val dataw = oSpi.io.dataw
val isEnR = oSpi.io.isEnR
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U )
cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U )
@@ -221,6 +258,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}.reverse
)
cReg.spiSel :=
RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h27".U & cReg.mstOrSlv === 0.U )
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )