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减少一半采样点，代码风格优化换面积

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RuigeLee
2024-05-09 11:06:41 +08:00
parent 0eb7e7b15b
commit 2ded26a706
1 changed files with 40 additions and 36 deletions
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52
src/main/scala/backBoard/LocalRegisters.scala
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@@ -92,12 +92,10 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
val LED_PR = IO(Output( Bool() )) val LED_PR = IO(Output( Bool() ))
LED_PR := ~Mux1H(Seq( LED_PR := ~Mux( statusPR === "b00".U, flash2HZ,
( statusPR === "b00".U ) -> flash2HZ, Mux( statusPR === "b01".U, flash1HZ,
( statusPR === "b01".U ) -> flash1HZ, Mux( statusPR === "b10".U, true.B, false.B
( statusPR === "b10".U ) -> true.B, )))
( statusPR === "b11".U ) -> false.B,
))
} }
@@ -107,7 +105,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
val inPin = Wire(UInt(16.W)) val inPin = Wire(UInt(16.W))
val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(3.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
val flitTrigger = Wire(Vec(9, Bool())) val flitTrigger = Wire(Vec(9, Bool()))
val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) } val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) } val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
@@ -115,7 +113,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
flitTrigger(0) := ~RegNext(flitTrigger(0)) flitTrigger(0) := ~RegNext(flitTrigger(0))
flitTrigger(1) := flitCnt(1) === 7.U flitTrigger(1) := flitCnt(1) === 15.U
when( ~RegNext(usTrigger) & usTrigger ){ when( ~RegNext(usTrigger) & usTrigger ){
flitCnt(1) := flitCnt(1) + 1.U flitCnt(1) := flitCnt(1) + 1.U
} }
@@ -162,42 +160,48 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
for( i <- 0 until 8 ) { for( i <- 0 until 8 ) {
for( j <- 0 until 2 ) { for( j <- 0 until 2 ) {
val flitter = RegInit(VecInit( Seq.fill(32){false.B})) val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
val flitHi = RegInit(0.U((log2Ceil(32)).W)) val flitHi = RegInit(0.U((log2Ceil(16)).W))
val shiftIn = RegNext( inPin(i+8*j) ) val shiftIn = RegNext( inPin(i+8*j) )
( 0 until 9 ).map{ k => val sample =
when( digitalFilter(j) === k.U ){ Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){ Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
))))))))
when( sample ){
flitter(0) := shiftIn flitter(0) := shiftIn
(1 until 32).map{ k => (1 until 16).map{ k =>
flitter(k) := flitter(k-1) flitter(k) := flitter(k-1)
} }
when( (~flitter(31) & ~flitter(0)) | (flitter(31) & flitter(0)) ){ when( ~flitter(15) & flitter(0) ){
flitHi := flitHi
} .elsewhen( ~flitter(31) & flitter(0) ){
flitHi := flitHi + 1.U flitHi := flitHi + 1.U
} .elsewhen( flitter(31) & ~flitter(0) ){ } .elsewhen( flitter(15) & ~flitter(0) ){
flitHi := flitHi - 1.U flitHi := flitHi - 1.U
} }
when( flitHi >= 25.U ){ when( flitHi === 12.U ){
digitalIn(j)(i) := true.B digitalIn(j)(i) := true.B
} .elsewhen( flitHi <= 6.U ){ } .elsewhen( flitHi === 3.U ){
digitalIn(j)(i) := false.B digitalIn(j)(i) := false.B
} }
// val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) ) // val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )
// assert( flitHi <= 31.U ) // assert( flitHi <= 15.U )
// assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi ) // assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
} }
} }
} }
}
}
} }