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16相位改8相位

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This commit is contained in:
Ruige Lee
2025-08-15 10:45:10 +08:00
parent fc917054ed
commit 2da45138db
2 changed files with 7 additions and 7 deletions
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12
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(16, Bool())))
val multiCLK = IO(Input(Vec(8, Bool())))
val sampleReg = Wire(Vec(23, Bool()))
val sampleReg = Wire(Vec(11, Bool()))
for( i <- 0 until 16 ) {
for( i <- 0 until 8 ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
}
for( i <- 16 until 23 ){
sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))}
for( i <- 8 until 11 ){
sampleReg(i) := withClockAndReset(multiCLK(i-4+1).asClock, reset.asBool){ RegNext(sampleReg(i-4+1))}
}
val asyncSerDat = PopCount(sampleReg) >= 12.U
val asyncSerDat = PopCount(sampleReg) >= 6.U
// sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U