diff --git a/Makefile b/Makefile index 65abac1..cd81313 100644 --- a/Makefile +++ b/Makefile @@ -12,29 +12,9 @@ endif .PHONY: compile tb wave -compile: - rm -rf ./generated/Rtpp - rm -rf ./rocket-chip/vsim/generated-src/ - mkdir -p ./generated/Rtpp - cd ./rocket-chip/ && rm -f rocketchip.jar - cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig - sed -e "s/CoreID = _RAND/\/\/CoreID = _RAND/g" ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v > ./generated/Rtpp/RtppConfig.v -# cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v - cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v - cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig/MirrorSRAMDP.v ./generated/Rtpp/MirrorSRAMDP.v -# sbt "test:runMain test.testModule" -back: - rm -f ./generated/back/* - rm -f ./generated/cdr/* - sbt "test:runMain test.testModule" - cp ./src/main/verilog/backBoardMstTop.v ./generated/back/ - cp ./src/main/verilog/oser_rst.v ./generated/back/ - cp ./src/main/verilog/di16_top.v ./generated/back/ - cp ./src/main/verilog/do16c_top.v ./generated/back/ - cp ./src/main/verilog/do16p_top.v ./generated/back/ - cp ./src/main/verilog/spi_top.v ./generated/back/ - cp ./src/main/verilog/defineParam.v ./generated/back/ + + shin: rm -f ./generated/shin/* @@ -110,207 +90,6 @@ fstShinClk: ef: sbt "test:runMain test.testModule" -VSimTop: - rm -rf ./tb/build/ - mkdir -p ./tb/build/ - verilator -Wno-fatal \ - -y ${PWD}/generated/Rtpp/ \ - -y ${PWD}/tb/verilator/ \ - --top-module SimTop \ - --trace \ - --trace-fst \ - --cc ./tb/verilator/SimTop.v \ - --cc ${PWD}/generated/Rtpp/behav_srams.v \ - --cc ${PWD}/generated/Rtpp/RtppConfig.v \ - --cc ${PWD}/generated/Rtpp/MirrorSRAMDP.v \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_DELAY=0 \ - --exe --build \ - ${PWD}/tb/verilator/sim_main.cpp \ - -Mdir ./tb/build/ \ - -j 30 - - # +define+RANDOMIZE_MEM_INIT - -test: - @echo "Start simulation..." - -./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest >./tb/sw/build/log.txt 2>&1 - @echo "done! Use the 'make fst' to view the simulation results." - @echo "Processing simulation log..." - @cat ./tb/sw/build/log.txt | grep '^\[\ \ 0\]' 1>./tb/sw/build/cpu0_log.txt - @cat ./tb/sw/build/log.txt | grep '^\[\ \ 1\]' 1>./tb/sw/build/cpu1_log.txt - @cat ./tb/sw/build/log.txt | grep '^\[\ \ 2\]' 1>./tb/sw/build/cpu2_log.txt - @cat ./tb/sw/build/log.txt | grep '^\[\ \ 3\]' 1>./tb/sw/build/cpu3_log.txt - @echo "done! Please check ./tb/sw/build/*log.txt" - -sw: - rm ./tb/sw/build/* -f - mkdir -p ./tb/sw/build/ - -#这是主站的中断服务程序，以及初始化程序 - $(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/hlmSvrOpt.S \ - -o ./tb/sw/build/hlmSvrOpt.o - - $(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ - -T ./tb/sw/linker.lds \ - ./tb/sw/build/hlmSvrOpt.o \ - -o ./tb/sw/build/hlmSvrOpt.elf - - $(TARGET)-objcopy -O binary ./tb/sw/build/hlmSvrOpt.elf ./tb/sw/build/hlmSvrOpt.bin - - python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/hlmSvrOpt.bin ./tb/sw/build/hlmSvrOpt.c - -#这是主站的程序 - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/build/hlmSvrOpt.c \ - -o ./tb/sw/build/hlmSvrOpt.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/mstStartup.S \ - -o ./tb/sw/build/mstStartup.o - - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/clint.c \ - -o ./tb/sw/build/clint.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/halfLvdsMacSvr.c \ - -o ./tb/sw/build/halfLvdsMacSvr.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/plic.c \ - -o ./tb/sw/build/plic.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/tl2cdr/tl2cdr.c \ - -o ./tb/sw/build/tl2cdr.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/MstMain.c \ - -o ./tb/sw/build/mstMain.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ - -T ./tb/sw/linker.lds \ - ./tb/sw/build/mstStartup.o \ - ./tb/sw/build/mstMain.o \ - ./tb/sw/build/hlmSvrOpt.o \ - ./tb/sw/build/tl2cdr.o \ - ./tb/sw/build/halfLvdsMacSvr.o \ - ./tb/sw/build/plic.o \ - ./tb/sw/build/clint.o \ - -o ./tb/sw/build/mstTest.elf - - $(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin - - $(TARGET)-objdump --disassemble-all -S --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump - - $(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog - sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog - -#这是从站的中断服务程序，以及初始化程序 - #$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ - #-I ./tb/sw/ -I ./tb/sw/src \ - #-I ./tb/sw/tl2cdr \ - #-c ./tb/sw/src/slvSvr.S \ - #-o ./tb/sw/build/slvSvr.o - - #$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ - #-T ./tb/sw/linker.lds \ - #./tb/sw/build/slvSvr.o \ - #-o ./tb/sw/build/slvSvr.elf - - #$(TARGET)-objcopy -O binary ./tb/sw/build/slvSvr.elf ./tb/sw/build/slvSvr.bin - - #python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/slvSvr.bin ./tb/sw/build/slvSvr.c - -#这是从站的程序 - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/build/hlmSvrOpt.c \ - -o ./tb/sw/build/hlmSvrOpt.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/tl2cdr/tl2cdr.c \ - -o ./tb/sw/build/tl2cdr.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/clint.c \ - -o ./tb/sw/build/clint.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/halfLvdsMacSvr.c \ - -o ./tb/sw/build/halfLvdsMacSvr.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/plic.c \ - -o ./tb/sw/build/plic.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/SlvMain.c \ - -o ./tb/sw/build/slvMain.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ - -I ./tb/sw/ -I ./tb/sw/src \ - -I ./tb/sw/tl2cdr \ - -c ./tb/sw/src/slvStartup.S \ - -o ./tb/sw/build/slvStartup.o - - $(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ - -T ./tb/sw/linker.lds \ - ./tb/sw/build/hlmSvrOpt.o \ - ./tb/sw/build/slvStartup.o \ - ./tb/sw/build/slvMain.o \ - ./tb/sw/build/tl2cdr.o \ - ./tb/sw/build/halfLvdsMacSvr.o \ - ./tb/sw/build/plic.o \ - ./tb/sw/build/clint.o \ - -o ./tb/sw/build/slvTest.elf - - $(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin - - $(TARGET)-objdump -S --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump - - $(TARGET)-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog - sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog - - python3 ./tb/sw/bin_to_hex.py - python3 ./tb/sw/bin_to_coe.py - - $(TARGET)-size ./tb/sw/build/mstTest.elf - - $(TARGET)-size ./tb/sw/build/slvTest.elf - fst: gtkwave ./tb/build/wave.fst & @@ -319,39 +98,6 @@ debug_hlm: -VSimBack: - rm -rf ./tb/build/ - mkdir -p ./tb/build/ - verilator -Wno-fatal \ - --timescale "1 ns / 1 ps" \ - -y ${PWD}/tb/ \ - -y ${PWD}/generated/ \ - --top-module BackPlaneChainTest \ - --trace-fst \ - --cc ./generated/BackPlaneChainTest.v \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_DELAY=0 \ - --exe --build \ - ${PWD}/tb/sim_backChain.cpp \ - -Mdir ./tb/build/ \ - -j 30 -# tb: -# iverilog -Wall \ -# -o ./build/wave.iverilog \ -# -y ./tb \ -# -y ./generated/cdr/ \ -# -I ./tb \ -# -I ./generated/cdr/ \ -# -D RANDOMIZE_REG_INIT \ -# ./tb/backSys_tb.v -# vvp -N ./build/wave.iverilog -lxt2 - -# vcd: -# gtkwave ./build/wave.vcd & - diff --git a/build.sbt b/build.sbt index 820ff71..ba957e5 100644 --- a/build.sbt +++ b/build.sbt @@ -40,77 +40,6 @@ def freshProject(name: String, dir: File): Project = { ) } -// Rocket-chip dependencies (subsumes making RC a RootProject) -lazy val hardfloat = (project in file("./rocket-chip/hardfloat")) - .settings(chiselSettings) - .settings(commonSettings) - .settings(name := "hardfloat", organization := "edu.berkeley.cs") - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - -lazy val rocketMacros = (project in file("./rocket-chip/macros")) - .settings(chiselSettings) - .settings(commonSettings) - .settings(name := "rocketMacros", organization := "org.chipsalliance") - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - -lazy val rocketConfig = (project in file("./rocket-chip/cde/cde/src/chipsalliance/rocketchip")) - .settings(chiselSettings) - .settings(commonSettings) - .settings(name := "rocketConfig", organization := "org.chipsalliance") - .settings(commonSettings) - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - -lazy val rocketchip = freshProject("rocketchip", file("./rocket-chip")) - .dependsOn(hardfloat, rocketMacros, rocketConfig) - .settings(commonSettings) - .settings(chiselSettings) - .settings(name := "rocketchip", organization := "org.chipsalliance", version := "1.6") - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - .settings( // Settings for scalafix - semanticdbEnabled := true, - semanticdbVersion := "4.7.6", - scalacOptions += "-Ywarn-unused" - ) -lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) - -lazy val blocks = (project in file("./rocket-chip-blocks")) - .dependsOn(rocketchip) - .settings(chiselSettings) - .settings(commonSettings) - .settings(name := "blocks", organization := "org.chipsalliance") - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - - lazy val root = (project in file("."))