diff --git a/.vscode/settings.json b/.vscode/settings.json
index 32cfc61..d39b29e 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -1,5 +1,9 @@
 {
     "files.watcherExclude": {
         "**/target": true
+    },
+    "files.associations": {
+        "system_cfg.h": "c",
+        "plic.h": "c"
     }
 }
\ No newline at end of file
diff --git a/Makefile b/Makefile
index 054bb83..18a52ac 100644
--- a/Makefile
+++ b/Makefile
@@ -48,6 +48,7 @@ VSimTop:
 	-y ${PWD}/generated/Rtpp/ \
 	-y ${PWD}/tb/verilator/ \
 	--top-module SimTop \
+	--trace \
 	--trace-fst \
 	--cc ./tb/verilator/SimTop.v  \
 	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
diff --git a/tb/sw/src/halfLvdsMacSvr.c b/tb/sw/src/halfLvdsMacSvr.c
index 6f26ccd..92f9c95 100644
--- a/tb/sw/src/halfLvdsMacSvr.c
+++ b/tb/sw/src/halfLvdsMacSvr.c
@@ -130,8 +130,6 @@ uint32_t HLM_poll(uint32_t mode)
 				if (rx_pkt_len <= (rx_index * 4))
 				{
 					rx_start = 0;
-					*rx0_softReset = 1;
-					*tx1_softReset = 1;
 				}
 			}
 
@@ -165,7 +163,7 @@ uint32_t HLM_poll(uint32_t mode)
 		{
 			//status = *HLM_status;
 
-			if (rx_start) // && (status & HLM_RX0_VALID))
+			if (rx_start)// && (status & HLM_RX0_VALID))
 			{
 				uint32_t data;
 				data = *rx0_rxFifo;
@@ -180,6 +178,19 @@ uint32_t HLM_poll(uint32_t mode)
 				if (rx_pkt_len <= (rx_index * 4))
 				{
 					rx_start = 0;
+					#if 0
+					*plic_enable_0_31 =   1 << CDR_INT_TX0END
+						| 1 << CDR_INT_TX1END
+
+						| 1 << CDR_INT_RX0ERROR
+						| 1 << CDR_INT_RX1ERROR
+
+						| 1 << CDR_INT_RX0START
+						| 1 << CDR_INT_RX1START
+
+						| 1 << CDR_INT_RX0END
+						| 1 << CDR_INT_RX1END;
+					#endif
 				}
 			}
 
@@ -188,8 +199,9 @@ uint32_t HLM_poll(uint32_t mode)
 			{
 				isr_flag[CDR_INT_RX0START] = 0;
 				rx_start = 1;
+				//*plic_enable_0_31 = 0;
 			}
-
+		#if 0
 			//rx1 上行
 			if (isr_flag[CDR_INT_RX1START])
 			{
@@ -207,6 +219,7 @@ uint32_t HLM_poll(uint32_t mode)
 				isr_flag[CDR_INT_RX1END] = 0;
 				//break;
 			}
+		#endif
 		}
 	}
 	else