Merge branch 'eb_dev' into mp_eb_dev
# Conflicts: # src/main/scala/backBoard/shin/Interface.scala # src/main/scala/backBoard/shin/ShinTop.scala # tb/shinTest/ShinTopSpiTb.v # tb/shinTest/gen_pkt.py # tb/shinTest/testcase/base.py
This commit is contained in:
Ruige Lee
@@ -77,9 +77,16 @@ class CommonRegisterBundle extends Bundle{
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val timeStamp = UInt(64.W)
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val mstDeltaTime = UInt(32.W)
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val syncCfg = UInt(8.W)
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val syncWidth = Vec(4, UInt(16.W) )
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val syncOffset = Vec(4, UInt(32.W))
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val syncPoint = UInt(64.W)
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val syncPeroid = UInt(32.W)
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val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
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val localPeroid = UInt(32.W)
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val localPoint = UInt(64.W)
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val custom = Vec( 128, UInt(8.W) )
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@@ -107,7 +114,7 @@ class MasterRegisterBundle extends Bundle{
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class SlaveRegisterBundle extends Bundle{
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val ebmmu = Vec(8, new EBMMU_Bundle)
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val ebmmu = Vec(16, new EBMMU_Bundle)
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val localDevIndex = UInt(16.W)
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@@ -120,12 +127,9 @@ class SlaveRegisterBundle extends Bundle{
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val slvDeltaTime = UInt(32.W) //从站时间戳差值
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val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
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val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
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val syncCfg = UInt(8.W)
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val syncWidth = Vec(4, UInt(16.W) )
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val syncOffset = Vec(4, UInt(32.W))
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}
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@@ -190,6 +194,7 @@ class InterfaceIO extends Bundle{
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val isSMReset = Output( Vec(8, Bool()) )
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val latchPin = Input(Vec(2, Bool()))
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val isPoReset = Output(Bool())
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}
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@@ -208,20 +213,7 @@ abstract class InterfaceBase extends Module{
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val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
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val sReg = Wire(new SlaveRegisterBundle); io.sReg := sReg
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val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
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val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
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for( i <- 0 until 4 ) {
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sReg.syncWidth(i) := syncWidth(i)
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}
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val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
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val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
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val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
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for( i <- 0 until 4 ) {
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sReg.syncOffset(i) := syncOffset(i)
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}
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@@ -378,28 +370,28 @@ abstract class InterfaceBase extends Module{
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(addr === "h117".U & isSlvMode) -> sReg.slvDeltaTime(31,24),
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//校准后的时钟
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(addr === "h118".U & isSlvMode) -> sReg.recoTimeStamp(7,0),
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(addr === "h119".U & isSlvMode) -> sReg.recoTimeStamp(15,8),
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(addr === "h11a".U & isSlvMode) -> sReg.recoTimeStamp(23,16),
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(addr === "h11b".U & isSlvMode) -> sReg.recoTimeStamp(31,24),
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(addr === "h11c".U & isSlvMode) -> sReg.recoTimeStamp(39,32),
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(addr === "h11d".U & isSlvMode) -> sReg.recoTimeStamp(47,40),
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(addr === "h11e".U & isSlvMode) -> sReg.recoTimeStamp(55,48),
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(addr === "h11f".U & isSlvMode) -> sReg.recoTimeStamp(63,56),
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(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
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(addr === "h119".U ) -> cReg.recoTimeStamp(15,8),
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(addr === "h11a".U ) -> cReg.recoTimeStamp(23,16),
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(addr === "h11b".U ) -> cReg.recoTimeStamp(31,24),
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(addr === "h11c".U ) -> cReg.recoTimeStamp(39,32),
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(addr === "h11d".U ) -> cReg.recoTimeStamp(47,40),
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(addr === "h11e".U ) -> cReg.recoTimeStamp(55,48),
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(addr === "h11f".U ) -> cReg.recoTimeStamp(63,56),
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(addr === "h120".U & isSlvMode) -> sReg.syncCfg,
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(addr === "h120".U ) -> cReg.syncCfg,
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(addr === "h122".U & isSlvMode) -> sReg.syncWidth(0)(7,0),
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(addr === "h123".U & isSlvMode) -> sReg.syncWidth(0)(15,8),
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(addr === "h122".U ) -> cReg.syncWidth(0)(7,0),
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(addr === "h123".U ) -> cReg.syncWidth(0)(15,8),
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(addr === "h124".U & isSlvMode) -> sReg.syncWidth(1)(7,0),
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(addr === "h125".U & isSlvMode) -> sReg.syncWidth(1)(15,8),
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(addr === "h124".U ) -> cReg.syncWidth(1)(7,0),
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(addr === "h125".U ) -> cReg.syncWidth(1)(15,8),
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(addr === "h126".U & isSlvMode) -> sReg.syncWidth(2)(7,0),
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(addr === "h127".U & isSlvMode) -> sReg.syncWidth(2)(15,8),
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(addr === "h126".U ) -> cReg.syncWidth(2)(7,0),
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(addr === "h127".U ) -> cReg.syncWidth(2)(15,8),
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(addr === "h128".U & isSlvMode) -> sReg.syncWidth(3)(7,0),
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(addr === "h129".U & isSlvMode) -> sReg.syncWidth(3)(15,8),
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(addr === "h128".U ) -> cReg.syncWidth(3)(7,0),
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(addr === "h129".U ) -> cReg.syncWidth(3)(15,8),
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(addr === "h130".U ) -> cReg.syncPoint(7,0),
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(addr === "h131".U ) -> cReg.syncPoint(15,8),
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@@ -415,25 +407,40 @@ abstract class InterfaceBase extends Module{
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(addr === "h13a".U ) -> cReg.syncPeroid(23,16),
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(addr === "h13b".U ) -> cReg.syncPeroid(31,24),
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(addr === "h13c".U & isSlvMode) -> sReg.syncOffset(1)(7,0),
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(addr === "h13d".U & isSlvMode) -> sReg.syncOffset(1)(15,8),
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(addr === "h13e".U & isSlvMode) -> sReg.syncOffset(1)(23,16),
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(addr === "h13f".U & isSlvMode) -> sReg.syncOffset(1)(31,24),
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(addr === "h13c".U ) -> cReg.syncOffset(1)(7,0),
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(addr === "h13d".U ) -> cReg.syncOffset(1)(15,8),
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(addr === "h13e".U ) -> cReg.syncOffset(1)(23,16),
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(addr === "h13f".U ) -> cReg.syncOffset(1)(31,24),
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(addr === "h140".U & isSlvMode) -> sReg.syncOffset(2)(7,0),
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(addr === "h141".U & isSlvMode) -> sReg.syncOffset(2)(15,8),
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(addr === "h142".U & isSlvMode) -> sReg.syncOffset(2)(23,16),
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(addr === "h143".U & isSlvMode) -> sReg.syncOffset(2)(31,24),
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(addr === "h140".U ) -> cReg.syncOffset(2)(7,0),
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(addr === "h141".U ) -> cReg.syncOffset(2)(15,8),
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(addr === "h142".U ) -> cReg.syncOffset(2)(23,16),
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(addr === "h143".U ) -> cReg.syncOffset(2)(31,24),
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(addr === "h144".U ) -> cReg.syncOffset(3)(7,0),
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(addr === "h145".U ) -> cReg.syncOffset(3)(15,8),
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(addr === "h146".U ) -> cReg.syncOffset(3)(23,16),
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(addr === "h147".U ) -> cReg.syncOffset(3)(31,24),
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(addr === "h148".U ) -> cReg.localPoint(7,0),
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(addr === "h149".U ) -> cReg.localPoint(15,8),
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(addr === "h14a".U ) -> cReg.localPoint(23,16),
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(addr === "h14b".U ) -> cReg.localPoint(31,24),
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(addr === "h14c".U ) -> cReg.localPoint(39,32),
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(addr === "h14d".U ) -> cReg.localPoint(47,40),
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(addr === "h14e".U ) -> cReg.localPoint(55,48),
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(addr === "h14f".U ) -> cReg.localPoint(63,56),
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(addr === "h150".U ) -> cReg.localPeroid(7,0),
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(addr === "h151".U ) -> cReg.localPeroid(15,8),
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(addr === "h152".U ) -> cReg.localPeroid(23,16),
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(addr === "h153".U ) -> cReg.localPeroid(31,24),
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(addr === "h144".U & isSlvMode) -> sReg.syncOffset(3)(7,0),
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(addr === "h145".U & isSlvMode) -> sReg.syncOffset(3)(15,8),
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(addr === "h146".U & isSlvMode) -> sReg.syncOffset(3)(23,16),
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(addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24),
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) ++
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( 0 until 128 ).map{ i =>
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( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i)
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} ++
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( 0 until 8 ).map{ i => Seq(
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( 0 until 16 ).map{ i => Seq(
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( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
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( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
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( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
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@@ -614,102 +621,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
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}
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when( isEnW & isSlvMode ){
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when( addrw === "h120".U ){
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syncCfg := dataw
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}
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for( i <- 0 until 4 ){
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when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
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syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
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} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
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syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
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}
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}
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when( addrw === "h130".U ){
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syncPoint := Cat( syncPoint(63,8), dataw )
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} .elsewhen( addrw === "h131".U ){
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syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
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} .elsewhen( addrw === "h132".U ){
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syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
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} .elsewhen( addrw === "h133".U ){
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syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
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} .elsewhen( addrw === "h134".U ){
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syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
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} .elsewhen( addrw === "h135".U ){
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syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
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} .elsewhen( addrw === "h136".U ){
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syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
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} .elsewhen( addrw === "h137".U ){
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syncPoint := Cat( dataw, syncPoint(55,0) )
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}
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.elsewhen( addrw === "h138".U ){
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syncPeroid := Cat( syncPeroid(31,8), dataw )
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} .elsewhen( addrw === "h139".U ){
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syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) )
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} .elsewhen( addrw === "h13a".U ){
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syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) )
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} .elsewhen( addrw === "h13b".U ){
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syncPeroid := Cat( dataw, syncPeroid(23,0) )
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}
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for( i <- 1 until 4 ){
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when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
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syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
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} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
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syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
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} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
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syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
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} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
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syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
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}
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}
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}
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val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
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cReg.wdtStatus := Cat( wdtStatus.reverse )
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for( i <- 0 until 8 ){
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when( isEnW & addrw === "h400".U & dataw.extract(i) ){
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wdtStatus(i) := false.B
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} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
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wdtStatus(i) := true.B
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}
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when( isEnW & addrw === "h401".U & dataw.extract(i) ){
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wdtStatus(8+i) := false.B
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} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
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wdtStatus(8+i) := true.B
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}
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}
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for( i <- 0 until 2 ){
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when( isEnW & addrw === "h402".U & dataw.extract(i) ){
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wdtStatus(16+i) := false.B
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} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
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wdtStatus(16+i) := true.B
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}
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}
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cReg.wdtEnable :=
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Cat(
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RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
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RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
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RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
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)
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for( i <- 0 until 18 ){
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cReg.wdtTarCnt(i) :=
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Cat(
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RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
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RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
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RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
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RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
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)
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}
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}
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trait InterfaceCheckSM{ this: InterfaceBase =>
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@@ -785,7 +696,140 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
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io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
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when( io.lvds.isEnW & isSlvMode ){
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( 0 until 16 ).map{ i =>
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sReg.ebmmu(i).lAddr := Cat(
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RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).pAddr := Cat(
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).length := Cat(
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
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)
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sReg.ebmmu(i).op :=
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RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
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sReg.ebmmu(i).isEnable :=
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RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
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}
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}
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trait InterfaceSync{ this: InterfaceBase =>
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val syncCfg = RegInit(0.U(8.W)); cReg.syncCfg := syncCfg
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val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
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for( i <- 0 until 4 ) {
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cReg.syncWidth(i) := syncWidth(i)
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}
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val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
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val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
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val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint
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val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid
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val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
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for( i <- 0 until 4 ) {
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cReg.syncOffset(i) := syncOffset(i)
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}
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when( isEnW ){
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when( addrw === "h120".U ){
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syncCfg := dataw
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}
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for( i <- 0 until 4 ){
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when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
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syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
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} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
|
||||
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
|
||||
}
|
||||
}
|
||||
|
||||
when( addrw === "h130".U ){
|
||||
syncPoint := Cat( syncPoint(63,8), dataw )
|
||||
} .elsewhen( addrw === "h131".U ){
|
||||
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
|
||||
} .elsewhen( addrw === "h132".U ){
|
||||
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
|
||||
} .elsewhen( addrw === "h133".U ){
|
||||
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
|
||||
} .elsewhen( addrw === "h134".U ){
|
||||
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
|
||||
} .elsewhen( addrw === "h135".U ){
|
||||
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
|
||||
} .elsewhen( addrw === "h136".U ){
|
||||
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
|
||||
} .elsewhen( addrw === "h137".U ){
|
||||
syncPoint := Cat( dataw, syncPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h138".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h139".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h13a".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h13b".U ){
|
||||
syncPeroid := Cat( dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h148".U ){
|
||||
localPoint := Cat( localPoint(63,8), dataw )
|
||||
} .elsewhen( addrw === "h149".U ){
|
||||
localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) )
|
||||
} .elsewhen( addrw === "h14a".U ){
|
||||
localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) )
|
||||
} .elsewhen( addrw === "h14b".U ){
|
||||
localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) )
|
||||
} .elsewhen( addrw === "h14c".U ){
|
||||
localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) )
|
||||
} .elsewhen( addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) )
|
||||
} .elsewhen( addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) )
|
||||
} .elsewhen( addrw === "h14f".U ){
|
||||
localPoint := Cat( dataw, localPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h153".U ){
|
||||
localPeroid := Cat( dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
|
||||
} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
|
||||
} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
|
||||
} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
when( io.lvds.isEnW ){
|
||||
|
||||
when( io.lvds.addrw === "h120".U ){
|
||||
syncCfg := io.lvds.dataw
|
||||
@@ -827,6 +871,35 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
|
||||
syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h148".U ){
|
||||
localPoint := Cat( localPoint(63,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h149".U ){
|
||||
localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14a".U ){
|
||||
localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14b".U ){
|
||||
localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14c".U ){
|
||||
localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14f".U ){
|
||||
localPoint := Cat( io.lvds.dataw, localPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h153".U ){
|
||||
localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
|
||||
@@ -840,43 +913,15 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
( 0 until 8 ).map{ i =>
|
||||
sReg.ebmmu(i).lAddr := Cat(
|
||||
RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).pAddr := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).length := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).op :=
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
|
||||
|
||||
sReg.ebmmu(i).isEnable :=
|
||||
RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceSync{ this: InterfaceBase =>
|
||||
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
|
||||
|
||||
cReg.mstDeltaTime := io.mstDeltaTime
|
||||
|
||||
|
||||
// sReg.mstTimeStamp := io.mstTimeStamp
|
||||
sReg.deltaFinal := io.deltaFinal
|
||||
sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
|
||||
cReg.recoTimeStamp :=
|
||||
Mux(isMstMode, cReg.timeStamp,
|
||||
RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
|
||||
)
|
||||
sReg.slvDeltaTime := io.slvDeltaTime
|
||||
|
||||
val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
|
||||
@@ -884,59 +929,101 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
|
||||
|
||||
|
||||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
syncSign(0) := true.B
|
||||
syncPoint := syncPoint + cReg.syncPeroid
|
||||
} .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
|
||||
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
|
||||
syncSign(0) := false.B
|
||||
} .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||||
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||||
syncSign(0) := false.B
|
||||
}
|
||||
|
||||
for( i <- 1 until 4 ) {
|
||||
|
||||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
syncOffsetCnt(i) := 0.U
|
||||
} .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
|
||||
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
|
||||
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
|
||||
} .elsewhen( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||||
} .elsewhen( syncOffsetCnt(i) === cReg.syncOffset(i) ){
|
||||
syncOffsetCnt(i) := "hFFFFFFFF".U(32.W)
|
||||
}
|
||||
|
||||
when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||||
when( syncOffsetCnt(i) === cReg.syncOffset(i) ){
|
||||
syncSign(i) := true.B
|
||||
} .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
|
||||
} .elsewhen( ~cReg.syncCfg(4+i) & syncResetCnt(i) === cReg.syncWidth(i) ){
|
||||
syncSign(i) := false.B
|
||||
} .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
|
||||
} .elsewhen( cReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
|
||||
syncSign(i) := false.B
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for( i <- 0 until 4 ){
|
||||
when( ~sReg.syncCfg(4+i) ){
|
||||
when( ~cReg.syncCfg(4+i) ){
|
||||
when( syncSign(i) ){
|
||||
syncResetCnt(i) := syncResetCnt(i) + 1.U
|
||||
} .otherwise{
|
||||
syncResetCnt(i) := 0.U
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
io.sync(0) := cReg.syncCfg.extract(0) & syncSign(0)
|
||||
io.sync(1) := cReg.syncCfg.extract(1) & syncSign(1)
|
||||
io.sync(2) := cReg.syncCfg.extract(2) & syncSign(2)
|
||||
io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)
|
||||
|
||||
|
||||
val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp
|
||||
|
||||
when( isLocalSyncInt ){ //时间到达localSync时间点
|
||||
localPoint := cReg.localPoint + cReg.localPeroid
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
|
||||
io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
|
||||
io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
|
||||
io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode
|
||||
|
||||
}
|
||||
|
||||
// trait InterfaceWdt{ this: InterfaceBase =>
|
||||
trait InterfaceWdt{ this: InterfaceBase =>
|
||||
val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
|
||||
cReg.wdtStatus := Cat( wdtStatus.reverse )
|
||||
|
||||
// }
|
||||
for( i <- 0 until 8 ){
|
||||
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
|
||||
wdtStatus(i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
|
||||
wdtStatus(i) := true.B
|
||||
}
|
||||
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
|
||||
wdtStatus(8+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
|
||||
wdtStatus(8+i) := true.B
|
||||
}
|
||||
}
|
||||
for( i <- 0 until 2 ){
|
||||
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
|
||||
wdtStatus(16+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
|
||||
wdtStatus(16+i) := true.B
|
||||
}
|
||||
}
|
||||
|
||||
cReg.wdtEnable :=
|
||||
Cat(
|
||||
RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
|
||||
)
|
||||
|
||||
for( i <- 0 until 18 ){
|
||||
cReg.wdtTarCnt(i) :=
|
||||
Cat(
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
trait InterfaceSystem{ this: InterfaceBase =>
|
||||
io.isSoftReset :=
|
||||
@@ -966,6 +1053,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
|
||||
}
|
||||
cReg.intStatus := Cat( intStatus.reverse )
|
||||
io.isPoReset := intStatus(31)
|
||||
|
||||
cReg.intMode :=
|
||||
Cat(
|
||||
@@ -988,7 +1076,19 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
}
|
||||
|
||||
//主站发送周期到了
|
||||
val isLocalSyncInt: Bool
|
||||
when( isLocalSyncInt ){
|
||||
intStatus(2) := true.B
|
||||
}
|
||||
|
||||
//外部latch中断
|
||||
val isLatchEvent =
|
||||
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
|
||||
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
|
||||
|
||||
when(isLatchEvent){
|
||||
intStatus(3) := true.B
|
||||
}
|
||||
|
||||
//看门狗溢出
|
||||
val isWdtTrigAndEnable = (0 until 18).map{ i => (io.wdtTrigger(i) & cReg.wdtEnable(i))}.reduce(_|_)
|
||||
@@ -1048,7 +1148,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
val trigIntPulse =
|
||||
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
|
||||
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
|
||||
false.B | //主站发送周期到了
|
||||
(isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了
|
||||
(isLatchEvent & cReg.intEnable(3)) | //latch Event
|
||||
(~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
|
||||
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
|
||||
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
|
||||
@@ -1074,8 +1175,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
|
||||
|
||||
trait InterfaceEvent{ this: InterfaceBase =>
|
||||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
|
||||
val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||||
val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||||
@@ -1277,7 +1378,7 @@ with InterfaceCheckSM
|
||||
with InterfaceLVDSop
|
||||
with InterfaceSync
|
||||
with InterfaceStat
|
||||
// with InterfaceWdt
|
||||
with InterfaceWdt
|
||||
with InterfaceSystem
|
||||
with InterfaceEvent
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user