Merge branch 'eb_dev' into mp_eb_dev
# Conflicts: # src/main/scala/backBoard/shin/Interface.scala # src/main/scala/backBoard/shin/ShinTop.scala # tb/shinTest/ShinTopSpiTb.v # tb/shinTest/gen_pkt.py # tb/shinTest/testcase/base.py
This commit is contained in:
Ruige Lee
@@ -77,9 +77,16 @@ class CommonRegisterBundle extends Bundle{
|
||||
|
||||
val timeStamp = UInt(64.W)
|
||||
val mstDeltaTime = UInt(32.W)
|
||||
|
||||
val syncCfg = UInt(8.W)
|
||||
val syncWidth = Vec(4, UInt(16.W) )
|
||||
val syncOffset = Vec(4, UInt(32.W))
|
||||
val syncPoint = UInt(64.W)
|
||||
val syncPeroid = UInt(32.W)
|
||||
val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
|
||||
|
||||
val localPeroid = UInt(32.W)
|
||||
val localPoint = UInt(64.W)
|
||||
|
||||
|
||||
val custom = Vec( 128, UInt(8.W) )
|
||||
|
||||
@@ -107,7 +114,7 @@ class MasterRegisterBundle extends Bundle{
|
||||
|
||||
|
||||
class SlaveRegisterBundle extends Bundle{
|
||||
val ebmmu = Vec(8, new EBMMU_Bundle)
|
||||
val ebmmu = Vec(16, new EBMMU_Bundle)
|
||||
|
||||
val localDevIndex = UInt(16.W)
|
||||
|
||||
@@ -120,12 +127,9 @@ class SlaveRegisterBundle extends Bundle{
|
||||
|
||||
val slvDeltaTime = UInt(32.W) //从站时间戳差值
|
||||
val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
|
||||
val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
|
||||
|
||||
val syncCfg = UInt(8.W)
|
||||
val syncWidth = Vec(4, UInt(16.W) )
|
||||
|
||||
val syncOffset = Vec(4, UInt(32.W))
|
||||
|
||||
|
||||
}
|
||||
|
||||
@@ -190,6 +194,7 @@ class InterfaceIO extends Bundle{
|
||||
val isSMReset = Output( Vec(8, Bool()) )
|
||||
|
||||
val latchPin = Input(Vec(2, Bool()))
|
||||
val isPoReset = Output(Bool())
|
||||
}
|
||||
|
||||
|
||||
@@ -208,20 +213,7 @@ abstract class InterfaceBase extends Module{
|
||||
val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
|
||||
val sReg = Wire(new SlaveRegisterBundle); io.sReg := sReg
|
||||
|
||||
val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
|
||||
|
||||
val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
|
||||
for( i <- 0 until 4 ) {
|
||||
sReg.syncWidth(i) := syncWidth(i)
|
||||
}
|
||||
|
||||
val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
|
||||
val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
|
||||
|
||||
val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
|
||||
for( i <- 0 until 4 ) {
|
||||
sReg.syncOffset(i) := syncOffset(i)
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -378,28 +370,28 @@ abstract class InterfaceBase extends Module{
|
||||
(addr === "h117".U & isSlvMode) -> sReg.slvDeltaTime(31,24),
|
||||
|
||||
//校准后的时钟
|
||||
(addr === "h118".U & isSlvMode) -> sReg.recoTimeStamp(7,0),
|
||||
(addr === "h119".U & isSlvMode) -> sReg.recoTimeStamp(15,8),
|
||||
(addr === "h11a".U & isSlvMode) -> sReg.recoTimeStamp(23,16),
|
||||
(addr === "h11b".U & isSlvMode) -> sReg.recoTimeStamp(31,24),
|
||||
(addr === "h11c".U & isSlvMode) -> sReg.recoTimeStamp(39,32),
|
||||
(addr === "h11d".U & isSlvMode) -> sReg.recoTimeStamp(47,40),
|
||||
(addr === "h11e".U & isSlvMode) -> sReg.recoTimeStamp(55,48),
|
||||
(addr === "h11f".U & isSlvMode) -> sReg.recoTimeStamp(63,56),
|
||||
(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
|
||||
(addr === "h119".U ) -> cReg.recoTimeStamp(15,8),
|
||||
(addr === "h11a".U ) -> cReg.recoTimeStamp(23,16),
|
||||
(addr === "h11b".U ) -> cReg.recoTimeStamp(31,24),
|
||||
(addr === "h11c".U ) -> cReg.recoTimeStamp(39,32),
|
||||
(addr === "h11d".U ) -> cReg.recoTimeStamp(47,40),
|
||||
(addr === "h11e".U ) -> cReg.recoTimeStamp(55,48),
|
||||
(addr === "h11f".U ) -> cReg.recoTimeStamp(63,56),
|
||||
|
||||
(addr === "h120".U & isSlvMode) -> sReg.syncCfg,
|
||||
(addr === "h120".U ) -> cReg.syncCfg,
|
||||
|
||||
(addr === "h122".U & isSlvMode) -> sReg.syncWidth(0)(7,0),
|
||||
(addr === "h123".U & isSlvMode) -> sReg.syncWidth(0)(15,8),
|
||||
(addr === "h122".U ) -> cReg.syncWidth(0)(7,0),
|
||||
(addr === "h123".U ) -> cReg.syncWidth(0)(15,8),
|
||||
|
||||
(addr === "h124".U & isSlvMode) -> sReg.syncWidth(1)(7,0),
|
||||
(addr === "h125".U & isSlvMode) -> sReg.syncWidth(1)(15,8),
|
||||
(addr === "h124".U ) -> cReg.syncWidth(1)(7,0),
|
||||
(addr === "h125".U ) -> cReg.syncWidth(1)(15,8),
|
||||
|
||||
(addr === "h126".U & isSlvMode) -> sReg.syncWidth(2)(7,0),
|
||||
(addr === "h127".U & isSlvMode) -> sReg.syncWidth(2)(15,8),
|
||||
(addr === "h126".U ) -> cReg.syncWidth(2)(7,0),
|
||||
(addr === "h127".U ) -> cReg.syncWidth(2)(15,8),
|
||||
|
||||
(addr === "h128".U & isSlvMode) -> sReg.syncWidth(3)(7,0),
|
||||
(addr === "h129".U & isSlvMode) -> sReg.syncWidth(3)(15,8),
|
||||
(addr === "h128".U ) -> cReg.syncWidth(3)(7,0),
|
||||
(addr === "h129".U ) -> cReg.syncWidth(3)(15,8),
|
||||
|
||||
(addr === "h130".U ) -> cReg.syncPoint(7,0),
|
||||
(addr === "h131".U ) -> cReg.syncPoint(15,8),
|
||||
@@ -415,25 +407,40 @@ abstract class InterfaceBase extends Module{
|
||||
(addr === "h13a".U ) -> cReg.syncPeroid(23,16),
|
||||
(addr === "h13b".U ) -> cReg.syncPeroid(31,24),
|
||||
|
||||
(addr === "h13c".U & isSlvMode) -> sReg.syncOffset(1)(7,0),
|
||||
(addr === "h13d".U & isSlvMode) -> sReg.syncOffset(1)(15,8),
|
||||
(addr === "h13e".U & isSlvMode) -> sReg.syncOffset(1)(23,16),
|
||||
(addr === "h13f".U & isSlvMode) -> sReg.syncOffset(1)(31,24),
|
||||
(addr === "h13c".U ) -> cReg.syncOffset(1)(7,0),
|
||||
(addr === "h13d".U ) -> cReg.syncOffset(1)(15,8),
|
||||
(addr === "h13e".U ) -> cReg.syncOffset(1)(23,16),
|
||||
(addr === "h13f".U ) -> cReg.syncOffset(1)(31,24),
|
||||
|
||||
(addr === "h140".U & isSlvMode) -> sReg.syncOffset(2)(7,0),
|
||||
(addr === "h141".U & isSlvMode) -> sReg.syncOffset(2)(15,8),
|
||||
(addr === "h142".U & isSlvMode) -> sReg.syncOffset(2)(23,16),
|
||||
(addr === "h143".U & isSlvMode) -> sReg.syncOffset(2)(31,24),
|
||||
(addr === "h140".U ) -> cReg.syncOffset(2)(7,0),
|
||||
(addr === "h141".U ) -> cReg.syncOffset(2)(15,8),
|
||||
(addr === "h142".U ) -> cReg.syncOffset(2)(23,16),
|
||||
(addr === "h143".U ) -> cReg.syncOffset(2)(31,24),
|
||||
|
||||
(addr === "h144".U ) -> cReg.syncOffset(3)(7,0),
|
||||
(addr === "h145".U ) -> cReg.syncOffset(3)(15,8),
|
||||
(addr === "h146".U ) -> cReg.syncOffset(3)(23,16),
|
||||
(addr === "h147".U ) -> cReg.syncOffset(3)(31,24),
|
||||
|
||||
(addr === "h148".U ) -> cReg.localPoint(7,0),
|
||||
(addr === "h149".U ) -> cReg.localPoint(15,8),
|
||||
(addr === "h14a".U ) -> cReg.localPoint(23,16),
|
||||
(addr === "h14b".U ) -> cReg.localPoint(31,24),
|
||||
(addr === "h14c".U ) -> cReg.localPoint(39,32),
|
||||
(addr === "h14d".U ) -> cReg.localPoint(47,40),
|
||||
(addr === "h14e".U ) -> cReg.localPoint(55,48),
|
||||
(addr === "h14f".U ) -> cReg.localPoint(63,56),
|
||||
|
||||
(addr === "h150".U ) -> cReg.localPeroid(7,0),
|
||||
(addr === "h151".U ) -> cReg.localPeroid(15,8),
|
||||
(addr === "h152".U ) -> cReg.localPeroid(23,16),
|
||||
(addr === "h153".U ) -> cReg.localPeroid(31,24),
|
||||
|
||||
(addr === "h144".U & isSlvMode) -> sReg.syncOffset(3)(7,0),
|
||||
(addr === "h145".U & isSlvMode) -> sReg.syncOffset(3)(15,8),
|
||||
(addr === "h146".U & isSlvMode) -> sReg.syncOffset(3)(23,16),
|
||||
(addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24),
|
||||
) ++
|
||||
( 0 until 128 ).map{ i =>
|
||||
( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i)
|
||||
} ++
|
||||
( 0 until 8 ).map{ i => Seq(
|
||||
( 0 until 16 ).map{ i => Seq(
|
||||
( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
|
||||
( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
|
||||
( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
|
||||
@@ -614,102 +621,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
|
||||
rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
|
||||
}
|
||||
|
||||
|
||||
when( isEnW & isSlvMode ){
|
||||
when( addrw === "h120".U ){
|
||||
syncCfg := dataw
|
||||
}
|
||||
|
||||
for( i <- 0 until 4 ){
|
||||
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
|
||||
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
|
||||
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
|
||||
}
|
||||
}
|
||||
|
||||
when( addrw === "h130".U ){
|
||||
syncPoint := Cat( syncPoint(63,8), dataw )
|
||||
} .elsewhen( addrw === "h131".U ){
|
||||
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
|
||||
} .elsewhen( addrw === "h132".U ){
|
||||
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
|
||||
} .elsewhen( addrw === "h133".U ){
|
||||
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
|
||||
} .elsewhen( addrw === "h134".U ){
|
||||
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
|
||||
} .elsewhen( addrw === "h135".U ){
|
||||
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
|
||||
} .elsewhen( addrw === "h136".U ){
|
||||
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
|
||||
} .elsewhen( addrw === "h137".U ){
|
||||
syncPoint := Cat( dataw, syncPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h138".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h139".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h13a".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h13b".U ){
|
||||
syncPeroid := Cat( dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
|
||||
} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
|
||||
} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
|
||||
} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
|
||||
cReg.wdtStatus := Cat( wdtStatus.reverse )
|
||||
|
||||
for( i <- 0 until 8 ){
|
||||
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
|
||||
wdtStatus(i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
|
||||
wdtStatus(i) := true.B
|
||||
}
|
||||
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
|
||||
wdtStatus(8+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
|
||||
wdtStatus(8+i) := true.B
|
||||
}
|
||||
}
|
||||
for( i <- 0 until 2 ){
|
||||
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
|
||||
wdtStatus(16+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
|
||||
wdtStatus(16+i) := true.B
|
||||
}
|
||||
}
|
||||
|
||||
cReg.wdtEnable :=
|
||||
Cat(
|
||||
RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
|
||||
)
|
||||
|
||||
for( i <- 0 until 18 ){
|
||||
cReg.wdtTarCnt(i) :=
|
||||
Cat(
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
|
||||
)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceCheckSM{ this: InterfaceBase =>
|
||||
@@ -785,7 +696,140 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
|
||||
|
||||
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
|
||||
|
||||
when( io.lvds.isEnW & isSlvMode ){
|
||||
|
||||
( 0 until 16 ).map{ i =>
|
||||
sReg.ebmmu(i).lAddr := Cat(
|
||||
RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).pAddr := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).length := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).op :=
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
|
||||
|
||||
sReg.ebmmu(i).isEnable :=
|
||||
RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceSync{ this: InterfaceBase =>
|
||||
|
||||
val syncCfg = RegInit(0.U(8.W)); cReg.syncCfg := syncCfg
|
||||
|
||||
val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
|
||||
for( i <- 0 until 4 ) {
|
||||
cReg.syncWidth(i) := syncWidth(i)
|
||||
}
|
||||
|
||||
val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
|
||||
val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
|
||||
val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint
|
||||
val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid
|
||||
|
||||
val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
|
||||
for( i <- 0 until 4 ) {
|
||||
cReg.syncOffset(i) := syncOffset(i)
|
||||
}
|
||||
|
||||
when( isEnW ){
|
||||
when( addrw === "h120".U ){
|
||||
syncCfg := dataw
|
||||
}
|
||||
|
||||
for( i <- 0 until 4 ){
|
||||
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
|
||||
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
|
||||
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
|
||||
}
|
||||
}
|
||||
|
||||
when( addrw === "h130".U ){
|
||||
syncPoint := Cat( syncPoint(63,8), dataw )
|
||||
} .elsewhen( addrw === "h131".U ){
|
||||
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
|
||||
} .elsewhen( addrw === "h132".U ){
|
||||
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
|
||||
} .elsewhen( addrw === "h133".U ){
|
||||
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
|
||||
} .elsewhen( addrw === "h134".U ){
|
||||
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
|
||||
} .elsewhen( addrw === "h135".U ){
|
||||
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
|
||||
} .elsewhen( addrw === "h136".U ){
|
||||
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
|
||||
} .elsewhen( addrw === "h137".U ){
|
||||
syncPoint := Cat( dataw, syncPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h138".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h139".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h13a".U ){
|
||||
syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h13b".U ){
|
||||
syncPeroid := Cat( dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h148".U ){
|
||||
localPoint := Cat( localPoint(63,8), dataw )
|
||||
} .elsewhen( addrw === "h149".U ){
|
||||
localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) )
|
||||
} .elsewhen( addrw === "h14a".U ){
|
||||
localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) )
|
||||
} .elsewhen( addrw === "h14b".U ){
|
||||
localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) )
|
||||
} .elsewhen( addrw === "h14c".U ){
|
||||
localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) )
|
||||
} .elsewhen( addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) )
|
||||
} .elsewhen( addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) )
|
||||
} .elsewhen( addrw === "h14f".U ){
|
||||
localPoint := Cat( dataw, localPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), dataw )
|
||||
} .elsewhen( addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) )
|
||||
} .elsewhen( addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) )
|
||||
} .elsewhen( addrw === "h153".U ){
|
||||
localPeroid := Cat( dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
|
||||
} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
|
||||
} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
|
||||
} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
when( io.lvds.isEnW ){
|
||||
|
||||
when( io.lvds.addrw === "h120".U ){
|
||||
syncCfg := io.lvds.dataw
|
||||
@@ -827,6 +871,35 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
|
||||
syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h148".U ){
|
||||
localPoint := Cat( localPoint(63,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h149".U ){
|
||||
localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14a".U ){
|
||||
localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14b".U ){
|
||||
localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14c".U ){
|
||||
localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14d".U ){
|
||||
localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14e".U ){
|
||||
localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h14f".U ){
|
||||
localPoint := Cat( io.lvds.dataw, localPoint(55,0) )
|
||||
}
|
||||
|
||||
.elsewhen( io.lvds.addrw === "h150".U ){
|
||||
localPeroid := Cat( localPeroid(31,8), io.lvds.dataw )
|
||||
} .elsewhen( io.lvds.addrw === "h151".U ){
|
||||
localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h152".U ){
|
||||
localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) )
|
||||
} .elsewhen( io.lvds.addrw === "h153".U ){
|
||||
localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) )
|
||||
}
|
||||
|
||||
|
||||
for( i <- 1 until 4 ){
|
||||
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
|
||||
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
|
||||
@@ -840,43 +913,15 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
( 0 until 8 ).map{ i =>
|
||||
sReg.ebmmu(i).lAddr := Cat(
|
||||
RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).pAddr := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).length := Cat(
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
|
||||
)
|
||||
|
||||
sReg.ebmmu(i).op :=
|
||||
RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
|
||||
|
||||
sReg.ebmmu(i).isEnable :=
|
||||
RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
trait InterfaceSync{ this: InterfaceBase =>
|
||||
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
|
||||
|
||||
cReg.mstDeltaTime := io.mstDeltaTime
|
||||
|
||||
|
||||
// sReg.mstTimeStamp := io.mstTimeStamp
|
||||
sReg.deltaFinal := io.deltaFinal
|
||||
sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
|
||||
cReg.recoTimeStamp :=
|
||||
Mux(isMstMode, cReg.timeStamp,
|
||||
RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
|
||||
)
|
||||
sReg.slvDeltaTime := io.slvDeltaTime
|
||||
|
||||
val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
|
||||
@@ -884,59 +929,101 @@ trait InterfaceSync{ this: InterfaceBase =>
|
||||
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
|
||||
|
||||
|
||||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
syncSign(0) := true.B
|
||||
syncPoint := syncPoint + cReg.syncPeroid
|
||||
} .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
|
||||
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
|
||||
syncSign(0) := false.B
|
||||
} .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||||
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
|
||||
syncSign(0) := false.B
|
||||
}
|
||||
|
||||
for( i <- 1 until 4 ) {
|
||||
|
||||
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
|
||||
syncOffsetCnt(i) := 0.U
|
||||
} .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
|
||||
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
|
||||
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
|
||||
} .elsewhen( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||||
} .elsewhen( syncOffsetCnt(i) === cReg.syncOffset(i) ){
|
||||
syncOffsetCnt(i) := "hFFFFFFFF".U(32.W)
|
||||
}
|
||||
|
||||
when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
|
||||
when( syncOffsetCnt(i) === cReg.syncOffset(i) ){
|
||||
syncSign(i) := true.B
|
||||
} .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
|
||||
} .elsewhen( ~cReg.syncCfg(4+i) & syncResetCnt(i) === cReg.syncWidth(i) ){
|
||||
syncSign(i) := false.B
|
||||
} .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
|
||||
} .elsewhen( cReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
|
||||
syncSign(i) := false.B
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for( i <- 0 until 4 ){
|
||||
when( ~sReg.syncCfg(4+i) ){
|
||||
when( ~cReg.syncCfg(4+i) ){
|
||||
when( syncSign(i) ){
|
||||
syncResetCnt(i) := syncResetCnt(i) + 1.U
|
||||
} .otherwise{
|
||||
syncResetCnt(i) := 0.U
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
io.sync(0) := cReg.syncCfg.extract(0) & syncSign(0)
|
||||
io.sync(1) := cReg.syncCfg.extract(1) & syncSign(1)
|
||||
io.sync(2) := cReg.syncCfg.extract(2) & syncSign(2)
|
||||
io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)
|
||||
|
||||
|
||||
val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp
|
||||
|
||||
when( isLocalSyncInt ){ //时间到达localSync时间点
|
||||
localPoint := cReg.localPoint + cReg.localPeroid
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
|
||||
io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
|
||||
io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
|
||||
io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode
|
||||
|
||||
}
|
||||
|
||||
// trait InterfaceWdt{ this: InterfaceBase =>
|
||||
trait InterfaceWdt{ this: InterfaceBase =>
|
||||
val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
|
||||
cReg.wdtStatus := Cat( wdtStatus.reverse )
|
||||
|
||||
// }
|
||||
for( i <- 0 until 8 ){
|
||||
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
|
||||
wdtStatus(i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
|
||||
wdtStatus(i) := true.B
|
||||
}
|
||||
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
|
||||
wdtStatus(8+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
|
||||
wdtStatus(8+i) := true.B
|
||||
}
|
||||
}
|
||||
for( i <- 0 until 2 ){
|
||||
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
|
||||
wdtStatus(16+i) := false.B
|
||||
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
|
||||
wdtStatus(16+i) := true.B
|
||||
}
|
||||
}
|
||||
|
||||
cReg.wdtEnable :=
|
||||
Cat(
|
||||
RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
|
||||
)
|
||||
|
||||
for( i <- 0 until 18 ){
|
||||
cReg.wdtTarCnt(i) :=
|
||||
Cat(
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
|
||||
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
trait InterfaceSystem{ this: InterfaceBase =>
|
||||
io.isSoftReset :=
|
||||
@@ -966,6 +1053,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
|
||||
}
|
||||
cReg.intStatus := Cat( intStatus.reverse )
|
||||
io.isPoReset := intStatus(31)
|
||||
|
||||
cReg.intMode :=
|
||||
Cat(
|
||||
@@ -988,7 +1076,19 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
}
|
||||
|
||||
//主站发送周期到了
|
||||
val isLocalSyncInt: Bool
|
||||
when( isLocalSyncInt ){
|
||||
intStatus(2) := true.B
|
||||
}
|
||||
|
||||
//外部latch中断
|
||||
val isLatchEvent =
|
||||
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
|
||||
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
|
||||
|
||||
when(isLatchEvent){
|
||||
intStatus(3) := true.B
|
||||
}
|
||||
|
||||
//看门狗溢出
|
||||
val isWdtTrigAndEnable = (0 until 18).map{ i => (io.wdtTrigger(i) & cReg.wdtEnable(i))}.reduce(_|_)
|
||||
@@ -1048,7 +1148,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
val trigIntPulse =
|
||||
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
|
||||
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
|
||||
false.B | //主站发送周期到了
|
||||
(isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了
|
||||
(isLatchEvent & cReg.intEnable(3)) | //latch Event
|
||||
(~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
|
||||
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
|
||||
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
|
||||
@@ -1074,8 +1175,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
|
||||
|
||||
|
||||
trait InterfaceEvent{ this: InterfaceBase =>
|
||||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isPosedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(2), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
val isNegedgeOnce = for( i <- 0 until 2 ) yield RegEnable( dataw.extract(3), false.B, isEnW & ( addrw === ( "h500".U + (i*2).U ) ))
|
||||
|
||||
val isPosedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||||
val isNegedgeLatch = for( i <- 0 until 2 ) yield RegInit(false.B)
|
||||
@@ -1277,7 +1378,7 @@ with InterfaceCheckSM
|
||||
with InterfaceLVDSop
|
||||
with InterfaceSync
|
||||
with InterfaceStat
|
||||
// with InterfaceWdt
|
||||
with InterfaceWdt
|
||||
with InterfaceSystem
|
||||
with InterfaceEvent
|
||||
{
|
||||
|
||||
@@ -1,44 +0,0 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
||||
|
||||
// class SRAM2kFifoIO extends Bundle {
|
||||
// val sram = new SRAM2kIO
|
||||
|
||||
// val enq = Flipped(Decoupled(UInt(8.W)))
|
||||
// val deq = Decoupled(UInt(8.W))
|
||||
// }
|
||||
|
||||
// class SRAM2kFifo extends Module {
|
||||
// val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)
|
||||
|
||||
// val wptr = RegInit(0.U((11+1).W))
|
||||
// val rptr = RegInit(0.U((11+1).W))
|
||||
|
||||
// val isFull = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
|
||||
// val isEmpty = (wptr === rptr)
|
||||
|
||||
|
||||
// io.sram.addrr := rptr(10,0)
|
||||
// io.sram.addrw := wptr(10,0)
|
||||
|
||||
// io.sram.dataw := io.enq.bits
|
||||
// io.deq.bits := io.sram.datar
|
||||
// io.sram.enw := io.enq.fire
|
||||
// io.sram.enr := true.B
|
||||
|
||||
// io.enq.ready := ~isFull
|
||||
// io.deq.valid := ~isEmpty
|
||||
|
||||
// when( io.enq.fire ){
|
||||
// wptr := wptr + 1.U
|
||||
// }
|
||||
|
||||
// when( io.deq.fire ){
|
||||
// rptr := rptr + 1.U
|
||||
// }
|
||||
|
||||
// }
|
||||
@@ -1,328 +0,0 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
||||
|
||||
class Header_Info_Bundle extends Bundle{
|
||||
val length = UInt(12.W) // nlength * 8bits
|
||||
val operator = UInt(4.W)
|
||||
val param = Vec(3, UInt(16.W))
|
||||
|
||||
def init = operator === 0.U
|
||||
def sync = operator === 1.U
|
||||
def boardCast = operator === 2.U
|
||||
def uniCast = operator === 3.U
|
||||
}
|
||||
|
||||
|
||||
|
||||
// class FSMC_Port_Bundle extends Bundle{
|
||||
|
||||
// val ADIn = Input(UInt(16.W))
|
||||
// val ADOut = Output(UInt(16.W))
|
||||
// val ADOEn = Output(Bool())
|
||||
// val csn = Input(Bool())
|
||||
// val rdn = Input(Bool())
|
||||
// val wrn = Input(Bool())
|
||||
// val advn = Input(Bool())
|
||||
// }
|
||||
|
||||
class ShinMstIO_Bundle extends Bundle{
|
||||
val FSMC = new FSMC_Port_Bundle
|
||||
|
||||
val interrupt = Output(Bool())
|
||||
val testIO = Input(Bool())
|
||||
|
||||
val serOut = Output(Bool())
|
||||
val serIn = Input(Bool())
|
||||
val overCLK = Input(Bool())
|
||||
}
|
||||
|
||||
|
||||
|
||||
abstract class ShinMstPhyBase extends Module{
|
||||
val io: ShinMstIO_Bundle = IO(new ShinMstIO_Bundle)
|
||||
|
||||
val mirrorDown = Module(new MirrorSRAMDP())
|
||||
val mirrorUp = Module(new MirrorSRAMDP())
|
||||
val mirrorReg = Module(new MirrorSRAMDP())
|
||||
|
||||
val cdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
|
||||
val cdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
|
||||
|
||||
io.serOut := cdrOut.io.serDat
|
||||
cdrIn.io.serDat := io.serIn
|
||||
cdrIn.io.overCLK := io.overCLK
|
||||
|
||||
mirrorDown.io.clockA := clock.asBool
|
||||
mirrorDown.io.clockB := clock.asBool
|
||||
|
||||
mirrorUp.io.clockA := clock.asBool
|
||||
mirrorUp.io.clockB := clock.asBool
|
||||
|
||||
mirrorReg.io.clockA := clock.asBool
|
||||
mirrorReg.io.clockB := clock.asBool
|
||||
|
||||
mirrorReg.io.addrB := DontCare
|
||||
mirrorReg.io.datawB := DontCare
|
||||
mirrorReg.io.enwB := false.B
|
||||
mirrorReg.io.enrB := false.B
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait ShinMstSend{ this: ShinMstPhyBase =>
|
||||
|
||||
|
||||
val headByte = (new Header_Info_Bundle).getWidth/8
|
||||
|
||||
require( headByte == 8 )
|
||||
|
||||
val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
|
||||
|
||||
val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt
|
||||
cdrOut.io.axis <> cdrPendBuf.io.deq
|
||||
|
||||
val sendHeader = Wire( new Header_Info_Bundle )
|
||||
sendHeader.length := 512.U
|
||||
sendHeader.operator := 0.U
|
||||
sendHeader.param(0) := 0.U
|
||||
sendHeader.param(1) := 0.U
|
||||
sendHeader.param(2) := 0.U
|
||||
val sendHead = sendHeader.asUInt
|
||||
|
||||
/*
|
||||
|
||||
val sendHeader = Reg( new Header_Info_Bundle )
|
||||
val sendHead = sendHeader.asUInt
|
||||
|
||||
|
||||
|
||||
when( ~testIOShift(0) & io.testIO ){
|
||||
mirrorReg.io.addrB := 0.U
|
||||
mirrorReg.io.enrB := true.B
|
||||
} .elsewhen( ~testIOShift(1) & testIOShift(0) ){
|
||||
mirrorReg.io.addrB := 1.U
|
||||
mirrorReg.io.enrB := true.B
|
||||
|
||||
sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
|
||||
} .elsewhen( ~testIOShift(2) & testIOShift(1) ){
|
||||
mirrorReg.io.addrB := 2.U
|
||||
mirrorReg.io.enrB := true.B
|
||||
|
||||
sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
|
||||
} .elsewhen( ~testIOShift(3) & testIOShift(2) ){
|
||||
mirrorReg.io.addrB := 3.U
|
||||
mirrorReg.io.enrB := true.B
|
||||
|
||||
sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
|
||||
} .elsewhen( ~testIOShift(4) & testIOShift(3) ){
|
||||
sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
|
||||
|
||||
val isRecvEnd = Wire(Bool())
|
||||
val isTimeout = Wire(Bool())
|
||||
|
||||
|
||||
val sendStateNext = Wire( UInt(3.W) )
|
||||
val sendStateCurr = RegNext( sendStateNext, 0.U )
|
||||
|
||||
|
||||
|
||||
val sendCntNext = Wire( UInt(10.W) )
|
||||
val sendCntCurr = RegNext(sendCntNext)
|
||||
|
||||
sendStateNext := Mux1H(Seq(
|
||||
(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
|
||||
(sendStateCurr === 1.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (headByte-1).U, 2.U, 1.U ),
|
||||
(sendStateCurr === 2.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (sendHeader.length ) - 1.U, 3.U, 2.U ),
|
||||
(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
|
||||
))
|
||||
|
||||
sendCntNext := Mux1H(Seq(
|
||||
(sendStateCurr === 0.U) -> 0.U,
|
||||
(sendStateCurr === 1.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 2.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
|
||||
(sendStateCurr === 2.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 3.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
|
||||
|
||||
))
|
||||
|
||||
|
||||
cdrPendBuf.io.enq.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
|
||||
cdrPendBuf.io.enq.bits.tdata :=
|
||||
Mux1H(Seq(
|
||||
( sendStateCurr === 1.U ) -> (sendHead << (sendCntCurr << 3)).apply(63,56),
|
||||
( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ),
|
||||
))
|
||||
cdrPendBuf.io.enq.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length - 1.U )
|
||||
cdrPendBuf.io.enq.bits.tuser := false.B
|
||||
|
||||
mirrorDown.io.enwB := false.B
|
||||
mirrorDown.io.datawB := 0.U
|
||||
mirrorDown.io.enrB := sendStateNext === 2.U
|
||||
mirrorDown.io.addrB := sendCntNext >> 1
|
||||
|
||||
}
|
||||
|
||||
trait ShinMstRecv{ this: ShinMstPhyBase =>
|
||||
val headByte: Int
|
||||
def isSendTrig: Bool
|
||||
|
||||
val RecvStateIdle = 0.U
|
||||
val RecvStateArm = 1.U
|
||||
val RecvStateHead = 2.U
|
||||
val RecvStatePayLoad = 3.U
|
||||
val RecvStateCRC = 4.U
|
||||
val RecvStateDeArm = 5.U
|
||||
|
||||
|
||||
val recvStateNext = Wire( UInt(3.W) )
|
||||
val recvStateCurr = RegNext( recvStateNext, 0.U )
|
||||
|
||||
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance )
|
||||
cdrIn.io.axis <> upPendBuf.io.enq
|
||||
|
||||
val recvHeader = Reg( UInt( (new Header_Info_Bundle).getWidth.W) )
|
||||
|
||||
val recvCnt = Reg(UInt(10.W))
|
||||
|
||||
val recvLength = RegEnable(recvHeader(15,4), upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead ) & recvCnt === 3.U)
|
||||
|
||||
val isRecvEnd: Bool
|
||||
isRecvEnd := recvStateCurr === RecvStateDeArm
|
||||
io.interrupt := recvStateCurr === RecvStateDeArm
|
||||
|
||||
|
||||
recvStateNext := Mux1H(Seq(
|
||||
(recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE
|
||||
(recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm
|
||||
(recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
|
||||
(recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
|
||||
(recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc
|
||||
(recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm
|
||||
|
||||
))
|
||||
|
||||
when( recvStateCurr =/= recvStateNext ){
|
||||
recvCnt := 1.U
|
||||
} .elsewhen( upPendBuf.io.deq.fire ){
|
||||
recvCnt := recvCnt + 1.U
|
||||
}
|
||||
|
||||
when( upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead )) {
|
||||
recvHeader := Cat( recvHeader.tail(8), upPendBuf.io.deq.bits.tdata )
|
||||
}
|
||||
|
||||
upPendBuf.io.deq.ready :=
|
||||
recvStateCurr === RecvStateHead | recvStateCurr === RecvStatePayLoad | recvStateCurr === RecvStateCRC
|
||||
|
||||
|
||||
val isRecvError = RegInit(false.B)
|
||||
|
||||
when( recvStateCurr === RecvStateIdle & recvStateNext === RecvStateArm ){
|
||||
isRecvError := false.B
|
||||
} .elsewhen( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tuser ){
|
||||
isRecvError := true.B
|
||||
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
|
||||
} .elsewhen( recvStateCurr === RecvStateHead & recvStateNext === RecvStateDeArm ){
|
||||
isRecvError := true.B
|
||||
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
|
||||
} .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){
|
||||
isRecvError := true.B
|
||||
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
|
||||
} .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 4.U ){
|
||||
isRecvError := true.B
|
||||
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
val recvDataLatch = RegEnable( upPendBuf.io.deq.bits.tdata, upPendBuf.io.deq.fire & recvStateCurr === 3.U & recvCnt.extract(0) )
|
||||
|
||||
mirrorUp.io.enrB := false.B
|
||||
mirrorUp.io.enwB := upPendBuf.io.deq.fire & recvStateCurr === 3.U & ~recvCnt.extract(0)
|
||||
mirrorUp.io.datawB := Cat( upPendBuf.io.deq.bits.tdata, recvDataLatch )
|
||||
mirrorUp.io.addrB := recvCnt >> 1
|
||||
|
||||
val recvRamAddr = Reg(UInt(8.W))
|
||||
|
||||
when( recvStateCurr === 2.U ){
|
||||
recvRamAddr := 0.U
|
||||
} .elsewhen( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
|
||||
recvRamAddr := recvRamAddr + 1.U
|
||||
}
|
||||
|
||||
|
||||
mirrorReg.io.datawB := Mux1H(Seq(
|
||||
(recvStateCurr === 3.U & recvRamAddr === 0.U) -> (recvHeader >> 16*3),
|
||||
(recvStateCurr === 3.U & recvRamAddr === 1.U) -> (recvHeader >> 16*2),
|
||||
(recvStateCurr === 3.U & recvRamAddr === 2.U) -> (recvHeader >> 16*1),
|
||||
(recvStateCurr === 3.U & recvRamAddr === 3.U) -> (recvHeader >> 16*0),
|
||||
))
|
||||
|
||||
|
||||
when( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
|
||||
mirrorReg.io.addrB := recvRamAddr
|
||||
mirrorReg.io.enwB := true.B
|
||||
}
|
||||
|
||||
|
||||
val isTimeout: Bool
|
||||
isTimeout :=
|
||||
Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 5.U )._2
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
abstract class ShinMstLinkBase extends ShinMstPhyBase
|
||||
with ShinMstSend
|
||||
with ShinMstRecv
|
||||
|
||||
|
||||
trait ShinMstInterface{ this: ShinMstLinkBase =>
|
||||
|
||||
io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
|
||||
|
||||
val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
|
||||
|
||||
val isAccessSRAM = ~latchAddr.extract(11)
|
||||
val isAccessReg = latchAddr.extract(11)
|
||||
val isAccessDown = ~latchAddr.extract(10)
|
||||
val activeAddr = latchAddr(9,0)
|
||||
|
||||
mirrorDown.io.addrA := activeAddr
|
||||
mirrorDown.io.datawA := io.FSMC.ADIn
|
||||
mirrorDown.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown
|
||||
mirrorDown.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown
|
||||
|
||||
mirrorUp.io.addrA := activeAddr
|
||||
mirrorUp.io.datawA := io.FSMC.ADIn
|
||||
mirrorUp.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown
|
||||
mirrorUp.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown
|
||||
|
||||
mirrorReg.io.addrA := activeAddr
|
||||
mirrorReg.io.datawA := io.FSMC.ADIn
|
||||
mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
|
||||
mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
|
||||
|
||||
io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) )
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
class ShinMst extends ShinMstLinkBase
|
||||
with ShinMstInterface
|
||||
|
||||
@@ -1,586 +0,0 @@
|
||||
package BACK
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class ShinSlvIO_Bundle extends Bundle{
|
||||
|
||||
val isOnline = Output(Bool())
|
||||
val isLast = Input(Bool())
|
||||
val DCIn = Input(Bool())
|
||||
|
||||
val downSer = new Bundle{
|
||||
val out = Output(Bool())
|
||||
val in = Input(Bool())
|
||||
}
|
||||
val upSer = new Bundle{
|
||||
val out = Output(Bool())
|
||||
val in = Input(Bool())
|
||||
}
|
||||
|
||||
val overCLK = Input(Bool())
|
||||
|
||||
}
|
||||
|
||||
abstract class ShinSlvPhyBase extends Module{
|
||||
val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle)
|
||||
|
||||
val downStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
|
||||
val downStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
|
||||
|
||||
val upStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
|
||||
val upStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
|
||||
|
||||
io.downSer.out := downStreamCdrOut.io.serDat
|
||||
downStreamCdrIn.io.serDat := io.downSer.in
|
||||
downStreamCdrIn.io.overCLK := io.overCLK
|
||||
|
||||
io.upSer.out := upStreamCdrOut.io.serDat
|
||||
upStreamCdrIn.io.serDat := io.upSer.in
|
||||
upStreamCdrIn.io.overCLK := io.overCLK
|
||||
|
||||
io.isOnline := true.B
|
||||
|
||||
|
||||
val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
|
||||
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
|
||||
|
||||
val headByte = (new Header_Info_Bundle).getWidth/8
|
||||
require( headByte == 8 )
|
||||
require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n")
|
||||
|
||||
val OpInitByte = 8
|
||||
val OpBoardCastByte = 16
|
||||
val OpUniCastByte = 32
|
||||
|
||||
val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
|
||||
|
||||
val downForwardFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
|
||||
val upForwardFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
|
||||
|
||||
val isLastDevice = Wire(Bool())
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
|
||||
|
||||
val DownRecvStateIdle = 0.U
|
||||
val DownRecvStateOHead = 1.U
|
||||
val DownRecvStateSData = 2.U
|
||||
val DownRecvStateFData = 3.U
|
||||
val DownRecvStateCRC = 4.U
|
||||
|
||||
|
||||
val downOldHead = Reg( new Header_Info_Bundle )
|
||||
val downNewHead = Reg( new Header_Info_Bundle )
|
||||
val downNewHeadShift = Reg( new Header_Info_Bundle )
|
||||
|
||||
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
|
||||
downStreamCdrIn.io.axis <> downPendBuf.io.enq
|
||||
|
||||
val downRecvStateNext = Wire( UInt(3.W) )
|
||||
val downRecvStateCurr = RegNext( downRecvStateNext, 0.U )
|
||||
|
||||
val downRecvCnt = Reg(UInt(10.W))
|
||||
|
||||
|
||||
val downLocalDataByte = RegEnable(
|
||||
Mux1H(Seq(
|
||||
( downOldHead.asUInt(3,0) === 0.U) -> OpInitByte.U, ( downOldHead.asUInt(3,0) === 1.U) -> OpBoardCastByte.U, ( downOldHead.asUInt(3,0) === 2.U) -> OpUniCastByte.U,
|
||||
)), downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire & downRecvCnt === 3.U) //Timing Opt
|
||||
|
||||
val isDownStreamError = RegInit( false.B )
|
||||
|
||||
val downForwardDataByte = downNewHead.length
|
||||
|
||||
val isLastDevice: Bool
|
||||
|
||||
downRecvStateNext := Mux1H(Seq(
|
||||
(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downPendBuf.io.deq.valid, DownRecvStateOHead, DownRecvStateIdle ),
|
||||
(downRecvStateCurr === DownRecvStateOHead) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === ((headByte)).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
|
||||
(downRecvStateCurr === DownRecvStateSData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downLocalDataByte ), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
|
||||
(downRecvStateCurr === DownRecvStateFData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downForwardDataByte ) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
|
||||
(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
|
||||
))
|
||||
|
||||
when( downRecvStateCurr =/= downRecvStateNext ){
|
||||
downRecvCnt := 1.U
|
||||
} .elsewhen( downPendBuf.io.deq.fire ){
|
||||
downRecvCnt := downRecvCnt + 1.U
|
||||
}
|
||||
|
||||
//---------------
|
||||
|
||||
when( downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire ){
|
||||
downOldHead := Cat( downOldHead.asUInt.tail(8), downPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
|
||||
}
|
||||
|
||||
|
||||
//---------------
|
||||
val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
|
||||
when( isDownNewHeadCreated ){
|
||||
downNewHead.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
|
||||
downNewHead.operator := downOldHead.operator
|
||||
downNewHead.param := downOldHead.param
|
||||
}
|
||||
|
||||
|
||||
when( downRecvStateCurr === DownRecvStateSData & downPendBuf.io.deq.fire ){
|
||||
downRegTemp(downRecvCnt-1.U) := downPendBuf.io.deq.bits.tdata
|
||||
}
|
||||
|
||||
//---------------
|
||||
downForwardFifo.io.enq.valid :=
|
||||
downRecvStateCurr === DownRecvStateFData & downPendBuf.io.deq.fire & ~isLastDevice
|
||||
downForwardFifo.io.enq.bits.tdata := downPendBuf.io.deq.bits.tdata
|
||||
downForwardFifo.io.enq.bits.tuser := downPendBuf.io.deq.bits.tuser
|
||||
downForwardFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte) | downPendBuf.io.deq.bits.tlast
|
||||
|
||||
downPendBuf.io.deq.ready :=
|
||||
(downRecvStateCurr === DownRecvStateOHead) |
|
||||
(downRecvStateCurr === DownRecvStateSData) |
|
||||
(downRecvStateCurr === DownRecvStateFData) |
|
||||
(downRecvStateCurr === DownRecvStateCRC )
|
||||
|
||||
when( downRecvStateCurr === DownRecvStateIdle & downRecvStateNext === DownRecvStateOHead){
|
||||
isDownStreamError := false.B
|
||||
} .elsewhen( downForwardFifo.io.enq.fire & downForwardFifo.io.enq.bits.tuser ){
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvStateNext === DownRecvStateIdle ){
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateIdle ){
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( downRecvStateCurr === DownRecvStateCRC & downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast & downRecvCnt =/= 4.U ){
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误
|
||||
isDownStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
|
||||
} .elsewhen( isDownNewHeadCreated & isLastDevice & downOldHead.length =/= downLocalDataByte ){
|
||||
printf("Warning, Wrong Package Received in DownStream, SoftWare Check!\n")
|
||||
}
|
||||
|
||||
|
||||
|
||||
assert( ~(downRecvStateCurr === DownRecvStateFData & ~downForwardFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
|
||||
val DownSendStateIdle = 0.U
|
||||
val DownSendStateNHead = 1.U
|
||||
val DownSendStateFData = 2.U
|
||||
|
||||
val downSendCnt = Reg(UInt(10.W))
|
||||
|
||||
val isDownNewHeadCreated: Bool
|
||||
val isLastDevice: Bool
|
||||
val downForwardDataByte: UInt
|
||||
val downNewHead: Header_Info_Bundle
|
||||
val downNewHeadShift: Header_Info_Bundle
|
||||
val isDownStreamError: Bool
|
||||
|
||||
|
||||
val downSendStateNext = Wire( UInt(3.W) )
|
||||
val downSendStateCurr = RegNext( downSendStateNext, 0.U )
|
||||
|
||||
downSendStateNext := Mux1H(Seq(
|
||||
( downSendStateCurr === DownSendStateIdle ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ),
|
||||
( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ),
|
||||
( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte ) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
|
||||
))
|
||||
|
||||
when( downSendStateCurr =/= downSendStateNext ){
|
||||
downSendCnt := 1.U
|
||||
} .elsewhen( downStreamCdrOut.io.axis.fire ){
|
||||
downSendCnt := downSendCnt + 1.U
|
||||
}
|
||||
|
||||
downStreamCdrOut.io.axis.valid :=
|
||||
downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData
|
||||
|
||||
downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
|
||||
( downSendStateCurr === DownSendStateNHead ) -> downNewHeadShift.asUInt(63,56),
|
||||
( downSendStateCurr === DownSendStateFData ) -> downForwardFifo.io.deq.bits.tdata,
|
||||
))
|
||||
|
||||
val downOldHead: Header_Info_Bundle
|
||||
val downLocalDataByte: UInt
|
||||
when( isDownNewHeadCreated ){
|
||||
downNewHeadShift.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
|
||||
downNewHeadShift.operator := downOldHead.operator
|
||||
downNewHeadShift.param := downOldHead.param
|
||||
} .elsewhen( downStreamCdrOut.io.axis.fire & downSendStateCurr === DownSendStateNHead ){
|
||||
downNewHeadShift := (downNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
|
||||
}
|
||||
|
||||
downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tlast
|
||||
|
||||
|
||||
downStreamCdrOut.io.axis.bits.tuser :=
|
||||
(( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tuser ) |
|
||||
isDownStreamError
|
||||
|
||||
downForwardFifo.io.deq.ready :=
|
||||
downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready
|
||||
|
||||
assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )
|
||||
}
|
||||
|
||||
abstract class ShinSlvPhyDownStream extends ShinSlvPhyBase
|
||||
with ShinSlvPhyDownStreamRecv
|
||||
with ShinSlvPhyDownStreamSend{
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
|
||||
|
||||
val UpRecvStateIdle = 0.U
|
||||
val UpRecvStateOHead = 1.U
|
||||
val UpRecvStateFData = 2.U
|
||||
val UpRecvStateCRC = 3.U
|
||||
|
||||
val upOldHead = Reg( new Header_Info_Bundle )
|
||||
val upNewHead = Reg( new Header_Info_Bundle )
|
||||
|
||||
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
|
||||
upStreamCdrIn.io.axis <> upPendBuf.io.enq
|
||||
|
||||
val upRecvStateNext = Wire( UInt(3.W) )
|
||||
val upRecvStateCurr = RegNext( upRecvStateNext, 0.U )
|
||||
|
||||
val upRecvCnt = Reg(UInt(10.W))
|
||||
|
||||
val isLastDevice: Bool
|
||||
|
||||
upRecvStateNext := Mux1H(Seq(
|
||||
(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upPendBuf.io.deq.valid, UpRecvStateOHead, UpRecvStateIdle ),
|
||||
(upRecvStateCurr === UpRecvStateOHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === ((headByte)).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
|
||||
(upRecvStateCurr === UpRecvStateFData) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === (upOldHead.length), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
|
||||
(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
|
||||
))
|
||||
|
||||
when( upRecvStateCurr =/= upRecvStateNext){
|
||||
upRecvCnt := 1.U
|
||||
} .elsewhen( upPendBuf.io.deq.fire ){
|
||||
upRecvCnt := upRecvCnt + 1.U
|
||||
}
|
||||
|
||||
|
||||
|
||||
val isLastDownStreamEnd = ( isLastDevice & (downRecvStateCurr === DownRecvStateCRC & downRecvStateNext === DownRecvStateIdle))
|
||||
|
||||
|
||||
//---------------
|
||||
|
||||
when( (upRecvStateCurr === UpRecvStateOHead & upPendBuf.io.deq.fire) ){
|
||||
// upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
|
||||
|
||||
when( upRecvCnt === 1.U ) {
|
||||
upOldHead.length := upPendBuf.io.deq.bits.tdata
|
||||
} .elsewhen( upRecvCnt === 2.U ) {
|
||||
upOldHead.length := Cat( upOldHead.length, upPendBuf.io.deq.bits.tdata(7,4) )
|
||||
upOldHead.operator := upPendBuf.io.deq.bits.tdata(3,0)
|
||||
} .elsewhen( upRecvCnt === 3.U ){
|
||||
upOldHead.param(0) := upPendBuf.io.deq.bits.tdata
|
||||
} .elsewhen( upRecvCnt === 4.U ){
|
||||
upOldHead.param(0) := Cat( upOldHead.param(0), upPendBuf.io.deq.bits.tdata )
|
||||
} .elsewhen( upRecvCnt === 5.U ){
|
||||
upOldHead.param(1) := upPendBuf.io.deq.bits.tdata
|
||||
} .elsewhen( upRecvCnt === 6.U ){
|
||||
upOldHead.param(1) := Cat( upOldHead.param(1), upPendBuf.io.deq.bits.tdata )
|
||||
} .elsewhen( upRecvCnt === 7.U ){
|
||||
upOldHead.param(2) := upPendBuf.io.deq.bits.tdata
|
||||
} .elsewhen( upRecvCnt === 8.U ){
|
||||
upOldHead.param(2) := Cat( upOldHead.param(2), upPendBuf.io.deq.bits.tdata )
|
||||
}
|
||||
} .elsewhen( isLastDownStreamEnd ){
|
||||
upOldHead.operator := downOldHead.operator
|
||||
upOldHead.length := 0.U
|
||||
upOldHead.param := downOldHead.param
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//---------------
|
||||
|
||||
|
||||
val upLocalDataByte = Mux1H(Seq(
|
||||
(upOldHead.operator === 0.U) -> OpInitByte.U,
|
||||
(upOldHead.operator === 1.U) -> OpBoardCastByte.U,
|
||||
(upOldHead.operator === 2.U) -> OpUniCastByte.U,
|
||||
))
|
||||
|
||||
|
||||
|
||||
val isUpNewHeadCreated =
|
||||
RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateFData, false.B) | //补一拍
|
||||
RegNext(isLastDownStreamEnd, false.B)
|
||||
|
||||
when( isUpNewHeadCreated ){
|
||||
upNewHead.length := upOldHead.length + upLocalDataByte
|
||||
upNewHead.operator := upOldHead.operator
|
||||
upNewHead.param := upOldHead.param
|
||||
}
|
||||
|
||||
val upForwardDataByte = upOldHead.length
|
||||
|
||||
|
||||
|
||||
//---------------
|
||||
upForwardFifo.io.enq.valid :=
|
||||
upRecvStateCurr === UpRecvStateFData & upPendBuf.io.deq.fire
|
||||
upForwardFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
|
||||
upForwardFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
|
||||
upForwardFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte) | upPendBuf.io.deq.bits.tlast
|
||||
|
||||
|
||||
upPendBuf.io.deq.ready :=
|
||||
(upRecvStateCurr === UpRecvStateOHead) |
|
||||
(upRecvStateCurr === UpRecvStateFData) |
|
||||
(upRecvStateCurr === UpRecvStateCRC )
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val isUpStreamError = RegInit( false.B )
|
||||
|
||||
|
||||
when( (upRecvStateCurr === UpRecvStateIdle & upRecvStateNext === UpRecvStateOHead) | isLastDownStreamEnd ){
|
||||
isUpStreamError := false.B
|
||||
} .elsewhen( upForwardFifo.io.enq.fire & upForwardFifo.io.enq.bits.tuser ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateIdle ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 4.U ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
}
|
||||
|
||||
|
||||
|
||||
assert( ~(upRecvStateCurr === UpRecvStateFData & ~upForwardFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" )
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
|
||||
|
||||
|
||||
val UpSendStateIdle = 0.U
|
||||
val UpSendStateNHead = 1.U
|
||||
val UpSendStateLData = 2.U
|
||||
val UpSendStateFData = 3.U
|
||||
|
||||
|
||||
|
||||
val upSendStateNext = Wire( UInt(3.W) )
|
||||
val upSendStateCurr = RegNext( upSendStateNext, 0.U )
|
||||
|
||||
val upSendCnt = Reg(UInt(10.W))
|
||||
|
||||
val isUpNewHeadCreated: Bool
|
||||
val upLocalDataByte: UInt
|
||||
val isLastDevice: Bool
|
||||
val upForwardDataByte: UInt
|
||||
val upNewHead: Header_Info_Bundle
|
||||
val isUpStreamError: Bool
|
||||
|
||||
upSendStateNext := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateIdle ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
|
||||
( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)).U & upStreamCdrOut.io.axis.fire, UpSendStateLData, UpSendStateNHead),
|
||||
( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
|
||||
( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte) & upStreamCdrOut.io.axis.fire, UpSendStateIdle, UpSendStateFData),
|
||||
))
|
||||
|
||||
when( upSendStateCurr =/= upSendStateNext ){
|
||||
upSendCnt := 1.U
|
||||
} .elsewhen( upStreamCdrOut.io.axis.fire ){
|
||||
upSendCnt := upSendCnt + 1.U
|
||||
}
|
||||
|
||||
|
||||
val upNewHeadShift = Reg(new Header_Info_Bundle)
|
||||
|
||||
upStreamCdrOut.io.axis.valid :=
|
||||
upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateNHead ) -> upNewHeadShift.asUInt(63,56),
|
||||
( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt-1.U),
|
||||
( upSendStateCurr === UpSendStateFData ) -> upForwardFifo.io.deq.bits.tdata,
|
||||
))
|
||||
|
||||
val upOldHead: Header_Info_Bundle
|
||||
when( isUpNewHeadCreated ){
|
||||
upNewHeadShift.length := upOldHead.length + upLocalDataByte
|
||||
upNewHeadShift.operator := upOldHead.operator
|
||||
upNewHeadShift.param := upOldHead.param
|
||||
} .elsewhen( upStreamCdrOut.io.axis.fire & upSendStateCurr === UpSendStateNHead ){
|
||||
upNewHeadShift := (upNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
|
||||
}
|
||||
|
||||
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tlast
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tuser :=
|
||||
(( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tuser ) |
|
||||
isUpStreamError
|
||||
|
||||
upForwardFifo.io.deq.ready :=
|
||||
upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
|
||||
|
||||
assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
|
||||
assert( ~(upSendStateCurr === UpSendStateFData & ~upForwardFifo.io.deq.valid) )
|
||||
|
||||
val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle)
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyDownStream =>
|
||||
// val isLastDevice: Bool
|
||||
|
||||
|
||||
// }
|
||||
|
||||
|
||||
abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream
|
||||
with ShinSlvPhyUpStreamRecv
|
||||
with ShinSlvPhyUpStreamSend
|
||||
// with ShinSlvPhyCloseLoop
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
|
||||
//定义初始化任务
|
||||
//下行定长包，各从机计算所在位置，更新ip地址寄存器，最后一个暂时通过IO实现闭环
|
||||
//以下行包头解析时间，从机位置号，标定数据计算更新RTC时间寄存器
|
||||
//上行根据包长，从站确定尾部伙伴数量（备用），
|
||||
//以上行包头解析时间放置本地时间
|
||||
//更新末尾寄存器
|
||||
|
||||
//热拔出 可以通过 io自动闭环，通过返回包缩短识别
|
||||
//热插入 必须带回寄存器信息，重新初始化，多发尾数据将被抛弃
|
||||
|
||||
//初始化应该下发 64*8 byte数据 对应 length = 512为slv0 504为slv1 ...
|
||||
|
||||
|
||||
val isInit = RegInit(false.B)
|
||||
val isLastInit = RegInit(false.B)
|
||||
val slvID = Reg(UInt(7.W))
|
||||
val slvNum = Reg(UInt(7.W))
|
||||
val slvRTC = Reg(UInt(64.W))
|
||||
|
||||
isLastDevice := isLastInit | io.isLast
|
||||
|
||||
val isLegalInitDownHead =
|
||||
downOldHead.operator === 0.U &
|
||||
downOldHead.length(2,0) === "b000".U
|
||||
|
||||
val isDownUpdate = RegInit(false.B)
|
||||
val isUpUpdate = RegInit(false.B)
|
||||
|
||||
val isLastDownStreamEnd: Bool
|
||||
val isUpStreamEnd: Bool
|
||||
val upOldHead: Header_Info_Bundle
|
||||
val isUpNewHeadCreated: Bool
|
||||
|
||||
|
||||
when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
|
||||
slvID := 64.U - (downOldHead.length >> 3)
|
||||
isDownUpdate := true.B
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isDownUpdate := false.B
|
||||
}
|
||||
|
||||
when( isUpStreamEnd ){
|
||||
slvRTC := upOldHead.length >> 3 //Need Calibration
|
||||
} .otherwise{
|
||||
slvRTC := slvRTC + 1.U
|
||||
}
|
||||
|
||||
when( isLastDownStreamEnd & isLegalInitDownHead ){
|
||||
isLastInit := true.B
|
||||
} .elsewhen( isDownNewHeadCreated & isLegalInitDownHead ){
|
||||
isLastInit := false.B
|
||||
}
|
||||
|
||||
val isLegalInitUpHead =
|
||||
upOldHead.operator === 0.U &
|
||||
upOldHead.length(2,0) === "b000".U
|
||||
|
||||
when( isUpNewHeadCreated ){
|
||||
when( isLastDownStreamEnd ){
|
||||
slvNum := 65.U - (downOldHead.length >> 3)
|
||||
isUpUpdate := true.B
|
||||
} .elsewhen(isLegalInitUpHead){
|
||||
slvNum := (slvID + (upOldHead.length >> 3)) + 1.U
|
||||
isUpUpdate := true.B
|
||||
}
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isUpUpdate := false.B
|
||||
}
|
||||
|
||||
when( isUpStreamEnd ){
|
||||
isInit := ~isDownStreamError & ~isUpStreamError & isDownUpdate & isUpUpdate
|
||||
}
|
||||
|
||||
val upRegMuxInit = isLegalInitUpHead
|
||||
when( upRegMuxInit ){
|
||||
upReg(0) := slvRTC(7,0)
|
||||
upReg(1) := slvRTC(15,8)
|
||||
upReg(2) := slvRTC(23,16)
|
||||
upReg(3) := slvRTC(31,24)
|
||||
upReg(4) := slvRTC(39,32)
|
||||
upReg(5) := slvRTC(47,40)
|
||||
upReg(6) := slvRTC(55,48)
|
||||
upReg(7) := slvRTC(63,56)
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
class ShinSlvBase extends ShinSlvLinkBase
|
||||
with ShinSlvLinkInit
|
||||
with ShinSlvLinkBCast
|
||||
with ShinSlvLinkUCast{
|
||||
assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
|
||||
|
||||
|
||||
val led = IO(UInt(8.W))
|
||||
led := RegEnable( 1.U << slvID, 0.U, ~RegNext(isInit) & isInit)
|
||||
}
|
||||
|
||||
|
||||
@@ -454,7 +454,7 @@ with ShinTopSlave
|
||||
with ShinTopWatchDog{
|
||||
|
||||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) ){ //硬件错误
|
||||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||||
downCDRIn.io.serDat := false.B
|
||||
upCDRIn.io.serDat := false.B
|
||||
when( slaveParser.io.isLoop ){ //回环
|
||||
|
||||
@@ -448,20 +448,6 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// when( downRecParser.io.subMsgHeadReq.fire &
|
||||
// downRecParser.io.subMsgHeadReq.bits.devIndex === 0.U &
|
||||
// downRecParser.io.subMsgHeadReq.bits.style === 0.U &
|
||||
// downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
|
||||
// localDevIndex := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgHeadReq.bits.workCnt + 2.U)
|
||||
// when( isDownRecPing ){
|
||||
// downSubMsgHeadInfo(0).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// } .otherwise{ //pong
|
||||
// downSubMsgHeadInfo(1).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// }
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -520,19 +506,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
val isDownLgcAddrwAcquireTrans = //是否触发地址转换
|
||||
(downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
|
||||
(downTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
|
||||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
|
||||
}.reduce(_|_))
|
||||
|
||||
val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(0 until 16).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).pAddr
|
||||
}
|
||||
)
|
||||
|
||||
val acquireDownTransLen = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(0 until 16).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).length
|
||||
}
|
||||
@@ -645,19 +631,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
|
||||
(upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
|
||||
(upTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
|
||||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
|
||||
}.reduce(_|_))
|
||||
|
||||
val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(0 until 16).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).pAddr
|
||||
}
|
||||
)
|
||||
|
||||
val acquireUpTransLen = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(0 until 16).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).length
|
||||
}
|
||||
@@ -827,27 +813,6 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
|
||||
// when( upRecParser.io.subMsgTailReq.fire ){
|
||||
// when( isUpRecPing ){
|
||||
// //override
|
||||
// when(
|
||||
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
// ){ //自身包//读或读写
|
||||
// upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// } .otherwise{
|
||||
// //override
|
||||
// when(
|
||||
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
// ){ //自身包//读或读写 )
|
||||
// upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
//下行接收
|
||||
when( downRecParser.io.subMsgTailReq.fire ){
|
||||
when( isDownRecPing ){
|
||||
@@ -958,17 +923,9 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
|
||||
trait SlaveParserProbe{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
// val ProbeRecAim = 511.U
|
||||
val probeRecCnt = RegInit(0.U(9.W))
|
||||
val isWatchDogOverflow = probeRecCnt.andR
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// val isReadyToProbe_Pending = RegInit(false.B)
|
||||
|
||||
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
|
||||
isReadyToProbe := true.B
|
||||
when( downSendGen.io.stateCurr =/= STATE_IDLE ){
|
||||
@@ -986,10 +943,6 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
|
||||
isAckProbe := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
// val isLastDevice = RegInit(true.B)
|
||||
|
||||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||||
isLastDevice := false.B
|
||||
} .elsewhen( isWatchDogOverflow ){
|
||||
@@ -997,9 +950,6 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||||
probeRecCnt := 0.U
|
||||
} .elsewhen( isWatchDogOverflow ){
|
||||
@@ -1031,14 +981,6 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
|
||||
|
||||
io.isLoop := isLastDevice & ~isReadyToProbe
|
||||
|
||||
|
||||
// when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
|
||||
// isLastDevice := isLastDevice_Pending
|
||||
// }
|
||||
|
||||
// when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
|
||||
// isReadyToProbe := isReadyToProbe_Pending
|
||||
// }
|
||||
}
|
||||
|
||||
class SlaveParser extends SlaveParserBase
|
||||
@@ -1055,9 +997,6 @@ with SlaveParserProbe{
|
||||
upRecParser.reset := reset.asBool | io.intHWClr(1)
|
||||
upSendGen.reset := reset.asBool | io.intHWClr(1)
|
||||
|
||||
//downRecParser.io.resp := io.intHWClr(0)
|
||||
//upRecParser.io.resp := io.intHWClr(1)
|
||||
|
||||
io.downRecStat := downRecParser.io.stat
|
||||
io.upRecStat := upRecParser.io.stat
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user