From 2a7faafcfff2cac211e2928e357c16ac4682e875 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 12 Aug 2025 18:09:40 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E4=BD=8D=E5=AE=BD=E6=8E=A8?= =?UTF-8?q?=E6=96=AD=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 80 +++++++++---------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index b8b0791..7319745 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -539,8 +539,8 @@ abstract class InterfaceBase extends Module{ //spi信号 val addrr = Wire(UInt(16.W)) val addrw = Wire(UInt(16.W)) - val dataw = Wire( UInt(8.W) ) - val datar = Wire( UInt(8.W) ) + val dataw = Wire( UInt(8.W) ) + val datar = Wire( UInt(8.W) ) val isEnW = Wire(Bool()) val isEnR = Wire(Bool()) @@ -610,33 +610,33 @@ trait InterfaceMCUop{ this: InterfaceBase => - cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) + cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) - cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) - cReg.spiSel := RegEnable( dataw(1,0), 1.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) + cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) + cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.pllCtrl := Cat( - RegEnable( dataw, "b10000000".U, isEnW & addrw === "h1b".U ), - RegEnable( dataw, "b00000000".U, isEnW & addrw === "h1a".U ), - RegEnable( dataw, "b11000000".U, isEnW & addrw === "h19".U ), - RegEnable( dataw, "b01011101".U, isEnW & addrw === "h18".U ) + RegEnable( dataw, "b10000000".U(8.W), isEnW & addrw === "h1b".U ), + RegEnable( dataw, "b00000000".U(8.W), isEnW & addrw === "h1a".U ), + RegEnable( dataw, "b11000000".U(8.W), isEnW & addrw === "h19".U ), + RegEnable( dataw, "b01011101".U(8.W), isEnW & addrw === "h18".U ) ) cReg.xtal := Cat( 0.U(16.W), - RegEnable( dataw, "b00000101".U, isEnW & addrw === "h1d".U ), - RegEnable( dataw, "b00010101".U, isEnW & addrw === "h1c".U ) + RegEnable( dataw, "b00000101".U(8.W), isEnW & addrw === "h1d".U ), + RegEnable( dataw, "b00010101".U(8.W), isEnW & addrw === "h1c".U ) ) - mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U ) - mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U ) + mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U ) + mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U ) // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) ) ( 0 until 128 ).map{ i => - cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) ) + cReg.custom(i) := RegEnable( dataw, 0.U(8.W), isEnW & (addrw === ("h180".U(16.W) + i.U)) ) } val rplTimeStampTx = RegInit(0.U(16.W)) @@ -729,24 +729,24 @@ trait InterfaceLVDSop{ this: InterfaceBase => ( 0 until 16 ).map{ i => sReg.ebmmu(i).lAddr := Cat( - RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw(5,0), 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).pAddr := Cat( - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).length := Cat( - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), ) sReg.ebmmu(i).op := - RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + RegEnable( io.lvds.dataw, 0.U(8.W), io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) sReg.ebmmu(i).isEnable := RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) @@ -1039,18 +1039,18 @@ trait InterfaceWdt{ this: InterfaceBase => cReg.wdtEnable := Cat( - RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ), + RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h406".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h405".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h404".U ), ) for( i <- 0 until 18 ){ cReg.wdtTarCnt(i) := Cat( - RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ), - RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ), - RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ), - RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ), ) } } @@ -1062,10 +1062,10 @@ trait InterfaceSystem{ this: InterfaceBase => cReg.softResetCode(2) === "h66".U & cReg.softResetCode(3) === "h79".U - cReg.softResetCode(0) := RegEnable(dataw, 0.U, isEnW & addrw === "h40".U ) - cReg.softResetCode(1) := RegEnable(dataw, 0.U, isEnW & addrw === "h41".U ) - cReg.softResetCode(2) := RegEnable(dataw, 0.U, isEnW & addrw === "h42".U ) - cReg.softResetCode(3) := RegEnable(dataw, 0.U, isEnW & addrw === "h43".U ) + cReg.softResetCode(0) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h40".U ) + cReg.softResetCode(1) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h41".U ) + cReg.softResetCode(2) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h42".U ) + cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U ) cReg.intEnable := @@ -1073,10 +1073,10 @@ trait InterfaceSystem{ this: InterfaceBase => 1.U(1.W), //复位中断，时钟为1 //31 上电复位 1.U(1.W), //复位中断，时钟为1 //30 上行硬件错误 1.U(1.W), //复位中断，时钟为1 //29 下行硬件错误 - RegEnable( dataw(4,0), 0.U, isEnW & addrw === "h73".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ), + RegEnable( dataw(4,0), 0.U(5.W), isEnW & addrw === "h73".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h72".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h71".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h70".U ), ) val intStatus = for( i <- 0 until 32 ) yield { @@ -1087,8 +1087,8 @@ trait InterfaceSystem{ this: InterfaceBase => cReg.intMode := Cat( - RegEnable( dataw, 0.U, isEnW & addrw === "h7d".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h7c".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h7d".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h7c".U ), ) val isLevelInt = cReg.intMode.extract(15) === false.B