diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index ef91ef9..3272eb8 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -415,7 +415,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) )                                                 )
   )
 
-  when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
+  when( downRecParser.io.subMsgReq.fire & (
+    downRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
+    downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE |
+    downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
+    )
+  ){
     addrw := downRecParser.io.subMsgReq.bits.address
   } .elsewhen( isWrite & downRecParser.io.data.fire ){
     addrw := addrw + 1.U
@@ -497,7 +502,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
       upRecParser.io.data.fire )
 
-  when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
+  when( upRecParser.io.subMsgReq.fire & (
+      upRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
+      upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD |
+      upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
+    )
+  ){
     addrr := upRecParser.io.subMsgReq.bits.address
   } .elsewhen( isLvdsEnR ){
     addrr := addrr + 1.U
@@ -515,14 +525,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   when( ~isUpRecPing ){ //req fire 后 已经反相
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
-      Mux( upSubMsgInfo(0).devIndex === localDevIndex & (
-        upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   |
-        upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   |
-        upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD |
-        upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR
-      ),
-        upStreamData, upRecParser.io.data.bits)
-    upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
+      Mux( 
+        (( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(0).devIndex === localDevIndex) |
+        (  upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )
+      ,
+        upStreamData, upRecParser.io.data.bits
+      )
+      upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
 
     upRecFifo(1).io.enq.valid := false.B
     upRecFifo(1).io.enq.bits  := 0.U
@@ -532,14 +541,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
     upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(1).io.enq.bits  :=
-      Mux( upSubMsgInfo(1).devIndex === localDevIndex & (
-        upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   |
-        upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   |
-        upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD |
-        upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR
-      ),
-        upStreamData, upRecParser.io.data.bits)
-    upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
+      Mux( 
+        (( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(1).devIndex === localDevIndex) |
+        (  upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )
+      ,
+        upStreamData, upRecParser.io.data.bits
+      )
+      upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
 
   }