Din16需要修改滤波方案

Makefile

@@ -12,10 +12,15 @@ compile:
 # 	sbt "test:runMain test.testModule"
 
 back:
+	rm -f ./generated/*
 	sbt "test:runMain test.testModule"
 	cp ./src/main/verilog/backBoardMstTop.v ./generated/
-	cp ./src/main/verilog/backBoardSlvTop.v ./generated/
+	# cp ./src/main/verilog/backBoardSlvTop.v ./generated/
 	cp ./src/main/verilog/oser_rst.v ./generated/
+	cp ./src/main/verilog/di16_top.v ./generated/
+	cp ./src/main/verilog/defineParam.v ./generated/
+
+
 
 ef: 
 	sbt "test:runMain test.testModule"

src/main/scala/backBoard/LocalRegisters.scala

@@ -3,8 +3,169 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+class ManualParamBundle extends Bundle{
+  val vendorID = UInt( 16.W )
+  val moduleID = UInt( 16.W )
+  val hwVersion = UInt( 16.W )
+  val swVersion = UInt( 16.W )
+  val batchID  = UInt( 16.W )
+  val serial   = UInt( 48.W )
+}
 
-class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
+
+abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
+
+  def DATA_SINWR_ADDR   : UInt = "h00".U
+  def DATA_PERWR_ADDR   : UInt = "h02".U
+  def STATUSWR_ADDR     : UInt = "h04".U
+
+  def DATA_SINRD_ADDR   : UInt = "h00".U
+  def DATA_PERRD_ADDR   : UInt = "h02".U
+  def STATUSRD_ADDR     : UInt = "h04".U
+
+  def VENDORID_ADDR     : UInt = "h10".U
+  def MODULEID_ADDR     : UInt = "h12".U
+  def HVERSION_ADDR     : UInt = "h14".U
+  def SVERSION_ADDR     : UInt = "h16".U
+  def BATCHNUM_ADDR     : UInt = "h18".U
+  def SERIAL0_ADDR      : UInt = "h1a".U
+  def SERIAL1_ADDR      : UInt = "h1c".U
+  def SERIAL2_ADDR      : UInt = "h1e".U
+
+  val param = IO(Input( new ManualParamBundle ))
+
+  val rankNum    = downReg(4)
+  val statusLed  = downReg(5)(1,0)
+
+  val (us10Counter, us10Trigger) = Counter(Range(0, 500))
+
+  when( true.B ){
+
+
+    upReg(16) := param.vendorID(7,0)
+    upReg(17) := param.vendorID(15,8)
+
+    upReg(18) := param.moduleID(7,0)
+    upReg(19) := param.moduleID(15,8)
+
+    upReg(20) := param.hwVersion(7,0)
+    upReg(21) := param.hwVersion(15,8)
+
+    upReg(22) := param.swVersion(7,0)
+    upReg(23) := param.swVersion(15,8)
+
+    upReg(24) := param.batchID(7,0)
+    upReg(25) := param.batchID(15,8)
+
+    upReg(26) := param.serial(7,0)
+    upReg(27) := param.serial(15,8)
+    upReg(28) := param.serial(23,16)
+    upReg(29) := param.serial(31,24)
+    upReg(30) := param.serial(39,32)
+    upReg(31) := param.serial(47,40)    
+  }
+
+
+}
+
+trait BackBoardSlvStatusLed { this: BackBoardSlvLocal =>
+  val flashCounter = RegInit( 0.U( 20.W ) )
+
+  when( us10Trigger ){
+    when( flashCounter === 100000.U ){
+      flashCounter := 0.U
+    } .otherwise{
+      flashCounter := flashCounter + 1.U      
+    }
+  }
+
+  val flash1HZ = flashCounter.extract(19)
+  val flash2HZ = flashCounter.extract(18)
+
+  val LED_PR = IO(Output( Bool() ))
+
+  LED_PR := Mux1H(Seq(
+    ( statusLed === "b00".U ) -> flash2HZ,
+    ( statusLed === "b01".U ) -> flash1HZ, 
+    ( statusLed === "b10".U ) -> true.B,
+    ( statusLed === "b11".U ) -> false.B,
+    ))
+}
+
+
+
+trait BackBoardSlvIn { this: BackBoardSlvLocal =>
+
+  def gp: Int
+
+  val flitCfg = Seq(
+    ( 0.U  -> 0.S ),
+    ( 1.U  -> 10.S),
+    ( 2.U  -> 25.S),
+    ( 3.U  -> 50.S),
+    ( 4.U  -> 100.S),
+    ( 5.U  -> 200.S),
+    ( 6.U  -> 400.S),
+    ( 7.U  -> 800.S),
+    ( 8.U  -> 1600.S),
+    ( 9.U  -> 3200.S),
+    ( 10.U -> 6400.S),
+  )
+
+  val in = IO(Input(UInt((8*gp).W)))
+
+  val digitalIn = Reg( Vec( 8*gp, Bool() ) )
+  
+
+  for( j <- 0 until gp ) {
+    when( true.B ) { upReg( 2+j ) := Cat( ( 8*j+7 to 8*j ).map{ k => digitalIn(k) } ) }
+
+    val digitalFilter = downReg(0+j)
+
+    for( i <- 0 until 8 ) {
+      val toCnt = RegInit( 0.S( 16.W ) )
+
+      flitCfg.map{ ( cfg: (UInt,SInt) ) => 
+        when( digitalFilter === cfg._1 ){
+          when( in(i+8*j) ){
+            when( toCnt >= cfg._2 ){
+              toCnt := cfg._2
+              digitalIn(i+8*j) := true.B
+            } .otherwise{
+              toCnt := toCnt + 1.S
+            }
+          } .otherwise{
+            when( toCnt <= -cfg._2 ){
+              toCnt := -cfg._2
+              digitalIn(i+8*j) := false.B
+            } .otherwise{
+              toCnt := toCnt - 1.S
+            }
+          }
+        }        
+        
+      }
+    }
+  }
+
+}
+
+
+
+
+class DIn16 extends BackBoardSlvLocal
+with BackBoardSlvStatusLed
+with BackBoardSlvIn{
+  def gp = 2
+}
+
+
+
+
+
+
+
+class BackBoardSlvOut16 extends BackBoardSlvLocal{
   val in  = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
   val oe  = IO(Output(UInt(32.W)))
@@ -14,18 +175,12 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
   out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
   oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
 
-
   for( i <- 0 until 4 ) {
     upReg(i) := in( i*8+7,8*i )
   }
-
-
 }
 
 
-
-
-
 // trait LocalRegisters { this: BackBoardSlvBase =>
 //   val led = IO(Output(UInt(3.W)))
 //   val sw  = IO( Input(UInt(1.W)))

src/main/verilog/defineParam.v

@@ -0,0 +1,6 @@
+`define VENDORID  16'h1122
+`define MODULEID  16'h3344
+`define HWVERSION 16'h5566
+`define SWVERSION 16'h7788
+`define BATCHID   16'h99aa
+`define SERIAL    48'hbbccddeeff00

src/main/verilog/di16_top.v

@@ -0,0 +1,156 @@
+
+
+module di16_top(
+
+  input resetn,
+  input clock, 
+     
+  input  lvds_up_din_p,
+  input  lvds_up_din_n, 
+  output lvds_up_dout_p,
+  output lvds_up_dout_n,  
+           
+  input  lvds_down_din_p,
+  input  lvds_down_din_n,  
+  output lvds_down_dout_p,
+  output lvds_down_dout_n,
+
+  output        LED_PR,
+  input  [15:0] in
+
+);
+
+wire clk_400m;
+wire clk_400m_a;
+wire clk_100m_a;
+wire clk_50m_a;
+wire clk_10m_a;
+
+wire lock_o;
+wire reset_stop;
+wire reset_calib;
+
+reg rst_n;
+reg rstn_d;
+
+
+
+
+always@(posedge clk_10m_a) begin
+  rstn_d <= resetn;
+	rst_n <= rstn_d;
+end
+
+Gowin_PLLO Gowin_PLLO(
+  .lock(lock_o), 
+  .clkouta(clk_400m),
+  .clkin(clock)
+);
+
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(lvds_down_dout)
+);
+
+
+TLVDS_IBUF lvds_downstream_in(
+  .O(lvds_down_din),
+  .I(lvds_down_din_p),
+  .IB(lvds_down_din_n)
+);
+
+
+TLVDS_OBUF lvds_upstream_out(
+  .O(lvds_up_dout_p),
+  .OB(lvds_up_dout_n),
+  .I(lvds_up_dout)
+);
+
+
+TLVDS_IBUF lvds_upstream_in(
+  .O(lvds_up_din),
+  .I(lvds_up_din_p),
+  .IB(lvds_up_din_n)
+);
+
+
+DHCEN dhcen_inst2 (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
+);
+
+
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(rst_n),
+  .pll_lock(lock_o), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_400m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m_a)
+);
+
+
+defparam Inst2_CLKDIVC.DIV_MODE="2";
+defparam Inst2_CLKDIVC.GSREN="false";
+CLKDIV Inst2_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_100m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_50m_a)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE="5";
+defparam Inst5_CLKDIVC.GSREN="false";
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_50m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_10m_a)
+);
+
+DIn16 i_din16(
+  .reset(~rst_n),
+  .clock(clk_10m_a),
+  .io_reset_calib(reset_calib),
+  .io_oser_pclk(clk_10m_a),
+  .io_oser_fclk(clk_50m_a),
+  .io_ides_pclk(clk_100m_a),
+  .io_ides_fclk(clk_400m_a),
+
+  .io_lvds_down_din(lvds_down_din),
+  .io_lvds_down_dout(lvds_down_dout),
+  .io_lvds_up_din(lvds_up_din),
+  .io_lvds_up_dout(lvds_up_dout),
+
+  .param_vendorID(`VENDORID),
+  .param_moduleID(`MODULEID),
+  .param_hwVersion(`HWVERSION),
+  .param_swVersion(`SWVERSION),
+  .param_batchID(`BATCHID),
+  .param_serial(`SERIAL),
+  .LED_PR(LED_PR),
+  .in(in)
+);
+
+endmodule
+
+
+
+

src/test/scala/gcd/test.scala

@@ -17,10 +17,13 @@ object testModule extends App {
       ChiselGeneratorAnnotation(() => { new BackBoardMst }),
     ))
 
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
+  //     ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
-    ))
+  //   ))
 
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new DIn16 })
+    ))
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
   //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
   //   ))