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Din16需要修改滤波方案

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This commit is contained in:
RuigeLee
2024-04-07 10:30:02 +08:00
parent d3a17e50c2
commit 27f6a09314
5 changed files with 336 additions and 11 deletions
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9
src/test/scala/gcd/test.scala
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@@ -17,10 +17,13 @@ object testModule extends App {
ChiselGeneratorAnnotation(() => { new BackBoardMst }),
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DIn16 })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))