Din16需要修改滤波方案

2024-04-07 10:30:02 +08:00
parent d3a17e50c2
commit 27f6a09314
5 changed files with 336 additions and 11 deletions
--- a/src/main/verilog/defineParam.v
+++ b/src/main/verilog/defineParam.v
@@ -0,0 +1,6 @@
+`define VENDORID  16'h1122
+`define MODULEID  16'h3344
+`define HWVERSION 16'h5566
+`define SWVERSION 16'h7788
+`define BATCHID   16'h99aa
+`define SERIAL    48'hbbccddeeff00