Din16需要修改滤波方案

2024-04-07 10:30:02 +08:00
parent d3a17e50c2
commit 27f6a09314
5 changed files with 336 additions and 11 deletions
--- a/7
+++ b/7
@@ -12,10 +12,15 @@ compile:
 # 	sbt "test:runMain test.testModule"

 back:
+	rm -f ./generated/*
 	sbt "test:runMain test.testModule"
 	cp ./src/main/verilog/backBoardMstTop.v ./generated/
-	cp ./src/main/verilog/backBoardSlvTop.v ./generated/
+	# cp ./src/main/verilog/backBoardSlvTop.v ./generated/
 	cp ./src/main/verilog/oser_rst.v ./generated/
+	cp ./src/main/verilog/di16_top.v ./generated/
+	cp ./src/main/verilog/defineParam.v ./generated/
+
+

 ef: 
 	sbt "test:runMain test.testModule"