From 2750a8e2f7ab0aadb0b7f1df9405e6b37ab61e43 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 12 Nov 2024 17:52:36 +0800
Subject: [PATCH] =?UTF-8?q?=E8=A7=84=E8=8C=83=E8=B7=A8=E6=97=B6=E9=92=9F?=
 =?UTF-8?q?=E4=BF=9D=E6=8A=A4=EF=BC=8C=E6=9C=89=E6=95=88=E6=9E=9C?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index c1c5359..9e02f0c 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -40,9 +40,9 @@ trait CDRInOverSample{ this: CDRInBase =>
     isArbLock := false.B
   }
 
-  val syncSerDat = ShiftRegister( 
-    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
-    , 2 )
+  val syncSerDat = 
+    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
+    
 }