diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index c1c5359..9e02f0c 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -40,9 +40,9 @@ trait CDRInOverSample{ this: CDRInBase =>
     isArbLock := false.B
   }
 
-  val syncSerDat = ShiftRegister( 
-    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
-    , 2 )
+  val syncSerDat = 
+    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
+    
 }