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更新fpga的顶层文件

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This commit is contained in:
bacon
2026-05-29 08:55:50 +08:00
parent 39986b7039
commit 259a4ab2af
2 changed files with 94 additions and 75 deletions
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134
src/main/resources/FPGATop_MP_spi.v
View File

@@ -19,6 +19,7 @@
//
//////////////////////////////////////////////////////////////////////////////////
//bacon base project
module FPGATop(
input clkin,
@@ -49,9 +50,9 @@ module FPGATop(
//output spi_miso,
//input spi_csn,
input io_qspi_sck,
inout [3:0] io_qspi_data,
input io_qspi_csn,
(* keep="true" *)input io_qspi_sck,
(* keep="true" *)inout [3:0] io_qspi_data,
(* keep="true" *)input io_qspi_csn,
output interrupt,
output [3:0] io_led,
@@ -127,7 +128,7 @@ clk_wiz_3 i_clk_3
// .clk_out4(multiCLK[3]),
// .clk_out5(multiCLK[4]),
// .clk_out6(multiCLK[5]),
.locked(),
.clk_in1(clkin)
);
@@ -243,20 +244,20 @@ always @( posedge clk320M )begin
end
end
// proc_sys_reset_0 i_proc_sys_reset(
// .slowest_sync_clk(clk50M),
// .ext_reset_in(resetIn),
// .aux_reset_in(1'b0),
// .mb_debug_sys_rst(1'b0),
// .dcm_locked(1'b1),
// .mb_reset(),
// .bus_struct_reset(),
// .peripheral_reset(reset),
// .interconnect_aresetn(),
// .peripheral_aresetn()
// );
proc_sys_reset_0 i_proc_sys_reset(
.slowest_sync_clk(multiCLK[0]),
.ext_reset_in(resetIn),
.aux_reset_in(1'b0),
.mb_debug_sys_rst(1'b0),
.dcm_locked(1'b1),
.mb_reset(),
.bus_struct_reset(),
.peripheral_reset(reset),
.interconnect_aresetn(),
.peripheral_aresetn()
);
assign reset = resetIn;
//assign reset = resetIn;
wire iqspi_sck;
wire [3:0] iqspi_mosi;
@@ -276,11 +277,11 @@ wire [3:0] aqspi_miso;
wire aqspi_isDirIn;
wire aqspi_cs;
//wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire [3:0] isDirIn;
//wire qspi_cs;
wire vqspi_sck;
wire [3:0] vqspi_mosi;
wire [3:0] vqspi_miso;
wire vqspi_isDirIn;
wire vqspi_cs;
wire bqspi_sck;
wire [3:0] bqspi_mosi;
@@ -288,12 +289,11 @@ wire [3:0] bqspi_miso;
wire bqspi_isDirIn;
wire bqspi_cs;
wire vqspi_sck;
wire [3:0] vqspi_mosi;
wire [3:0] vqspi_miso;
wire vqspi_isDirIn;
wire vqspi_cs;
//wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire [3:0] isDirIn;
//wire qspi_cs;
wire [2:0] spi_sel;
@@ -344,18 +344,18 @@ ShinTop i_ShinTop(
.io_aqspi_isDirIn(aqspi_isDirIn),
.io_aqspi_csn(aqspi_cs),
.io_bqspi_sck(bqspi_sck),
.io_bqspi_mosi(bqspi_mosi),
.io_bqspi_miso(bqspi_miso),
.io_bqspi_isDirIn(bqspi_isDirIn),
.io_bqspi_csn(bqspi_cs),
.io_vqspi_sck(vqspi_sck),
.io_vqspi_mosi(vqspi_mosi),
.io_vqspi_miso(vqspi_miso),
.io_vqspi_isDirIn(vqspi_isDirIn),
.io_vqspi_csn(vqspi_cs),
.io_bqspi_sck(bqspi_sck),
.io_bqspi_mosi(bqspi_mosi),
.io_bqspi_miso(bqspi_miso),
.io_bqspi_isDirIn(bqspi_isDirIn),
.io_bqspi_csn(bqspi_cs),
.io_ospi_sck(spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
@@ -385,47 +385,57 @@ ShinTop i_ShinTop(
);
reg [2:0] spi_sel_post;
always @(posedge multiCLK[0]) begin
if (reset | isSoftReset) begin
spi_sel_post <= 3'b001;
end else if( io_qspi_csn ) begin
spi_sel_post <= spi_sel;
end
end
assign io_led = led[5:2];
assign testIO = 12'hfff;
assign iqspi_sck = (spi_sel == 3'b000)? io_qspi_sck : 1'b0;
assign spi_sck = (spi_sel == 3'b001)? io_qspi_sck : 1'b0;
assign oqspi_sck = (spi_sel == 3'b010)? io_qspi_sck : 1'b0;
assign aqspi_sck = (spi_sel == 3'b011)? io_qspi_sck : 1'b0;
assign vqspi_sck = (spi_sel == 3'b100)? io_qspi_sck : 1'b0;
assign bqspi_sck = (spi_sel == 3'b101)? io_qspi_sck : 1'b0;
assign iqspi_sck = (spi_sel_post == 3'b000)? io_qspi_sck : 1'b0;
assign spi_sck = (spi_sel_post == 3'b001)? io_qspi_sck : 1'b0;
assign oqspi_sck = (spi_sel_post == 3'b010)? io_qspi_sck : 1'b0;
assign aqspi_sck = (spi_sel_post == 3'b011)? io_qspi_sck : 1'b0;
assign vqspi_sck = (spi_sel_post == 3'b100)? io_qspi_sck : 1'b0;
assign bqspi_sck = (spi_sel_post == 3'b101)? io_qspi_sck : 1'b0;
assign iqspi_mosi = (spi_sel == 3'b000)? qspi_mosi : 4'b0;
assign spi_mosi = (spi_sel == 3'b001)? qspi_mosi[0] : 4'b0;
assign oqspi_mosi = (spi_sel == 3'b010)? qspi_mosi : 4'b0;
assign aqspi_mosi = (spi_sel == 3'b011)? qspi_mosi : 4'b0;
assign vqspi_mosi = (spi_sel == 3'b100)? qspi_mosi : 4'b0;
assign bqspi_mosi = (spi_sel == 3'b101)? qspi_mosi : 4'b0;
assign iqspi_mosi = (spi_sel_post == 3'b000)? qspi_mosi : 4'b0;
assign spi_mosi = (spi_sel_post == 3'b001)? qspi_mosi[0] : 4'b0;
assign oqspi_mosi = (spi_sel_post == 3'b010)? qspi_mosi : 4'b0;
assign aqspi_mosi = (spi_sel_post == 3'b011)? qspi_mosi : 4'b0;
assign vqspi_mosi = (spi_sel_post == 3'b100)? qspi_mosi : 4'b0;
assign bqspi_mosi = (spi_sel_post == 3'b101)? qspi_mosi : 4'b0;
assign qspi_miso = (spi_sel == 3'b000)? iqspi_miso :
(spi_sel == 3'b001)? {2'b0, spi_miso, 1'b0} :
(spi_sel == 3'b010)? oqspi_miso :
(spi_sel == 3'b011)? aqspi_miso :
(spi_sel == 3'b100)? vqspi_miso : bqspi_miso;
assign qspi_miso = (spi_sel_post == 3'b000)? iqspi_miso :
(spi_sel_post == 3'b001)? {2'b0, spi_miso, 1'b0} :
(spi_sel_post == 3'b010)? oqspi_miso :
(spi_sel_post == 3'b011)? aqspi_miso :
(spi_sel_post == 3'b100)? vqspi_miso : bqspi_miso;
assign iqspi_cs = (spi_sel == 3'b000)? io_qspi_csn : 1'b1;
assign spi_csn = (spi_sel == 3'b001)? io_qspi_csn : 1'b1;
assign oqspi_cs = (spi_sel == 3'b010)? io_qspi_csn : 1'b1;
assign aqspi_cs = (spi_sel == 3'b011)? io_qspi_csn : 1'b1;
assign vqspi_cs = (spi_sel == 3'b100)? io_qspi_csn : 1'b1;
assign bqspi_cs = (spi_sel == 3'b101)? io_qspi_csn : 1'b1;
assign iqspi_cs = (spi_sel_post == 3'b000)? io_qspi_csn : 1'b1;
assign spi_csn = (spi_sel_post == 3'b001)? io_qspi_csn : 1'b1;
assign oqspi_cs = (spi_sel_post == 3'b010)? io_qspi_csn : 1'b1;
assign aqspi_cs = (spi_sel_post == 3'b011)? io_qspi_csn : 1'b1;
assign vqspi_cs = (spi_sel_post == 3'b100)? io_qspi_csn : 1'b1;
assign bqspi_cs = (spi_sel_post == 3'b101)? io_qspi_csn : 1'b1;
assign isDirIn = (spi_sel == 3'b000)? {iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn} :
(spi_sel == 3'b001)? {2'b1, 1'b0, 1'b1} :
(spi_sel == 3'b010)? {oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn} :
(spi_sel == 3'b011)? {aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn} :
(spi_sel == 3'b100)? {vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn} :
assign isDirIn = (spi_sel_post == 3'b000)? {iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn} :
(spi_sel_post == 3'b001)? {2'b11, 1'b0, 1'b1} :
(spi_sel_post == 3'b010)? {oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn} :
(spi_sel_post == 3'b011)? {aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn} :
(spi_sel_post == 3'b100)? {vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn} :
{bqspi_isDirIn, bqspi_isDirIn, bqspi_isDirIn, bqspi_isDirIn};
IOBUF QSPI_D0_inst (
.O(qspi_mosi[0]), // Buffer output
.IO(io_qspi_data[0]), // Buffer inout port (connect directly to top-level port)

33
src/main/resources/constr_spi.xdc
View File

@@ -2,10 +2,10 @@ set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports clkin]
#CPUPC8
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports resetIn]
#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
#set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports spi_miso]
#set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports spi_sck]
#set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports spi_csn]
#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports mosi]
#set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports miso]
#set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports sck]
#set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports csn]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD TMDS_33} [get_ports dDatOut_p]
@@ -34,6 +34,12 @@ set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports latch1]
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports interrupt]
#set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports io_iqspi_sck]
#set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {io_iqspi_data[0]}]
#set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {io_iqspi_data[1]}]
#set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {io_iqspi_data[2]}]
#set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {io_iqspi_data[3]}]
#set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports io_iqspi_csn]
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports io_qspi_sck]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {io_qspi_data[0]}]
@@ -64,10 +70,6 @@ set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {testIO[11]}
#set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33} [get_ports {testIO[14]}]
#set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {testIO[15]}]
create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} [get_ports clkin]
create_clock -period 50.000 -name multi0 -waveform {0.000 25.000} [get_nets {multiCLK[0]}]
create_clock -period 50.000 -name multi1 -waveform {3.125 28.125} [get_nets {multiCLK[1]}]
create_clock -period 50.000 -name multi2 -waveform {6.250 31.250} [get_nets {multiCLK[2]}]
@@ -87,8 +89,15 @@ create_clock -period 50.000 -name multi15 -waveform {46.875 71.875} [get_nets {m
create_clock -period 100.000 -name sck_async -waveform {0.000 50.000} [get_nets i_ShinTop/aqspi_sck]
set_clock_groups -name async_group -asynchronous -group [get_clocks {multi0 multi1 multi2 multi3 multi4 multi5 multi6 multi7 multi8 multi9 multi10 multi11 multi12 multi13 multi14 multi15 sys_clk}] -group [get_clocks sck_async]
create_clock -period 50.000 -name qspiclk -waveform {0.000 25.000} [get_nets {i_ShinTop/aqspi_sck i_ShinTop/bqspi_sck}]
#set_clock_groups -name async -asynchronous -group [list [get_clocks -regexp .*multi.*] [get_clocks [list sys_clk [get_clocks -of_objects [get_pins i_clk_3/inst/mmcm_adv_inst/CLKOUT0]] [get_clocks -of_objects [get_pins i_clk_3/inst/mmcm_adv_inst/CLKFBOUT]]]]] -group [get_clocks qspiclk]
#set_max_delay -datapath_only -from [get_cells -hier -filter {CLOCK_NAME == qspiclk}] -to [get_cells -hier -filter {CLOCK_NAME == multi0}] 50.000
#set_max_delay -datapath_only -from [get_cells -hier -filter {CLOCK_NAME == multi0}] -to [get_cells -hier -filter {CLOCK_NAME == qspiclk}] 50.000
set_max_delay -datapath_only -from [get_clocks qspiclk] -to [get_clocks multi0] 50.000
set_max_delay -datapath_only -from [get_clocks multi0] -to [get_clocks qspiclk] 50.000
set_input_delay -clock [get_clocks sck_async] -clock_fall -min -20.000 [get_ports -regexp -filter { NAME =~ ".*qspi.*" && DIRECTION == "INOUT" }]
set_input_delay -clock [get_clocks sck_async] -clock_fall -max 20.000 [get_ports -regexp -filter { NAME =~ ".*qspi.*" && DIRECTION == "INOUT" }]