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successfully interger in rocketchip

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RuigeLee
2023-07-13 17:38:01 +08:00
parent 02ec89bda5
commit 25584bf6f5
4 changed files with 30 additions and 94 deletions
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9
src/main/scala/mac/MAC.scala
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@@ -15,11 +15,12 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x30000000L, 0x0FFFL)),
regionType = RegionType.UNCACHED,
regionType = RegionType.VOLATILE,
executable = false,
supportsGet = TransferSizes(32/8, 32/8),
supportsPutFull = TransferSizes(32/8, 32/8),
supportsPutPartial = TransferSizes(32/8, 32/8)
fifoId = Some(2),
supportsGet = TransferSizes(8/8, 32/8),
supportsPutFull = TransferSizes(8/8, 32/8),
supportsPutPartial = TransferSizes(8/8, 32/8)
)),
beatBytes = 32/8)))