From 242765f10638427c274df4358962ce2923a366ae Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 11 Jul 2023 23:05:44 +0800
Subject: [PATCH] add trait

---
 src/main/scala/def/def.scala     |  0
 src/main/scala/mac/WithMac.scala | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+)
 delete mode 100644 src/main/scala/def/def.scala
 create mode 100644 src/main/scala/mac/WithMac.scala

diff --git a/src/main/scala/def/def.scala b/src/main/scala/def/def.scala
deleted file mode 100644
index e69de29..0000000
diff --git a/src/main/scala/mac/WithMac.scala b/src/main/scala/mac/WithMac.scala
new file mode 100644
index 0000000..bd117df
--- /dev/null
+++ b/src/main/scala/mac/WithMac.scala
@@ -0,0 +1,19 @@
+package MAC
+
+import chisel3._
+import org.chipsalliance.cde.config.Field
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,BufferParams}
+import freechips.rocketchip.tilelink.{TLBuffer, TLIdentityNode, TLWidthWidget, TLFragmenter}
+
+
+trait WithManyMacMix { this: BaseSubsystem =>
+
+    val mac = LazyModule(new Mac)
+
+    fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac.tlClientNode }
+    pbus.coupleTo("mac_cfg") { mac.tlMasterNode := TLFragmenter(4, pbus.blockBytes) := TLWidthWidget(pbus.beatBytes) := _ }
+
+    ibus.fromSync := mac.int_node
+
+}
\ No newline at end of file