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微调spi访存时间点，提高理论极限频率

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RuigeLee
2025-09-09 16:10:19 +08:00
parent 2b1f01274b
commit 22cc6ef0b8
1 changed files with 13 additions and 13 deletions
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26
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -59,12 +59,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val byteSel = RegInit(0.U(12.W))
val byteSelNext = RegNext(byteSel, 0.U(12.W))
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
io.dataw := exRegi
io.addrr := addrr
io.addrw := addrw
when( shiftCSn(2) & ~shiftCSn(1) ){
byteSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
@@ -93,15 +93,14 @@ class SSpiInterface extends SpiInterfaceBase{
sck := spi.sck
csn := spi.csn
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === 1.U & byteSel === 2.U ) |
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U )
when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1)
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(2) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(2)
}
@@ -137,7 +136,6 @@ class SSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
@@ -145,7 +143,7 @@ class SSpiInterface extends SpiInterfaceBase{
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
@@ -173,13 +171,14 @@ class QSpiInterface extends SpiInterfaceBase{
qspi.miso := exRego(7, 4)
qspi.isDirIn := ~isSpiRead
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(2) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(2) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(2).extract(3)
}
@@ -213,6 +212,7 @@ class QSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
@@ -220,7 +220,7 @@ class QSpiInterface extends SpiInterfaceBase{
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}