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ethreg Test pass

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This commit is contained in:
RuigeLee
2023-07-21 16:38:02 +08:00
parent 0b48e2cd2b
commit 21f8547273
3 changed files with 32 additions and 32 deletions
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47
src/main/scala/mac/MacRegisters.scala
View File

@@ -137,7 +137,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
val minFL = RegInit("h0040".U(16.W))
val collValid = RegInit("h3f".U(6.W))
val maxRet = RegInit("hF".U(4.U))
val maxRet = RegInit("hF".U(4.W))
val TX_BD_NUM = RegInit("h40".U(8.W)) // TX_BD_NUM Register
@@ -232,20 +232,19 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
)),
( 6 << 2 ) ->
RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq(
RegField(16, maxFL, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))),
RegField(16, minFL, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))),
)),
RegFieldGroup("PACKETLEN", Some("Packet Length Register"),
RegField.bytes(maxFL, Some(RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600)))) ++
RegField.bytes(minFL, Some(RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))))
),
( 7 << 2 ) ->
RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))),
RegField.r(10,0.U),
RegField(4, maxRet, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))),
)),
( 8 << 2 ) ->
RegFieldGroup("TX_BD_NUM", Some("Transmit BD Number Register"), Seq(
RegField(8, TX_BD_NUM, RegFieldDesc("TX_BD_NUM", "TX_BD_NUM", reset=Some(0x40))),
RegField(8, TX_BD_NUM, RegWriteFn((valid, data) => { when (valid & data <= "h80".U) { TX_BD_NUM := data }; true.B }), RegFieldDesc("TX_BD_NUM", "TX_BD_NUM", reset=Some(0x40))),
)),
( 9 << 2 ) ->
@@ -276,9 +275,9 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
)),
( 13 << 2 ) ->
RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"), Seq(
RegField(16, MIITX_DATA)
)),
RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"),
RegField.bytes(MIITX_DATA)
),
( 14 << 2 ) ->
RegFieldGroup("MIIRX_DATA", Some("MII Receive Data"), Seq(
@@ -293,28 +292,28 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
)),
( 16 << 2 ) ->
RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
RegField(32, Mac_ADDR0)
)),
RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"),
RegField.bytes(Mac_ADDR0)
),
( 17 << 2 ) ->
RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
RegField(16, Mac_ADDR1)
)),
RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"),
RegField.bytes(Mac_ADDR1)
),
( 18 << 2 ) ->
RegFieldGroup("HASH0", Some("HASH Register 0"), Seq(
RegField(32, HASH0)
)),
RegFieldGroup("HASH0", Some("HASH Register 0"),
RegField.bytes(HASH0)
),
( 19 << 2 ) ->
RegFieldGroup("HASH1", Some("HASH Register 1"), Seq(
RegField(32, HASH1)
)),
RegFieldGroup("HASH1", Some("HASH Register 1"),
RegField.bytes(HASH1)
),
( 20 << 2 ) ->
RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq(
RegField(16, txPauseTV, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))),
RegFieldGroup("TXCTRL", Some("Tx Control Register"),
RegField.bytes(txPauseTV, Some(RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0)))) ++ Seq(
RegField(1, txPauseRq, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))),
)),
)

12
src/main/scala/mac/MacTilelink.scala
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@@ -988,13 +988,13 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
// Connected to registers
val CsMiss = Wire(Bool())
// val CsMiss = Wire(Bool())
BDCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x400 - 0x7FF
CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
BDCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x400 - 0x7FF
// CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
val slvAInfo = RegEnable( io.tlSlv.A.bits, io.tlSlv.A.fire )
val slvDValid = RegInit(false.B); io.tlSlv.D.valid := slvDValid
@@ -1018,9 +1018,9 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
io.tlSlv.A.ready := BDAck
assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) )
when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){
assert( false.B, "Assert Failed, tileLink access an undefine region!" )
}
// when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){
// assert( false.B, "Assert Failed, tileLink access an undefine region!" )
// }

5
src/test/scala/gcd/Mac_test_top.scala
View File

@@ -37,9 +37,10 @@ class MacTest(implicit p: Parameters) extends Mac{
))
)))
val tlBar = TLXbar()
val tlBar = TLXbar()
tlMasterNode := tlBar := tlClientIONode
tlBar := tlClientIONode
tlMasterNode := tlBar
ethReg.configNode := tlBar
val intSinkNode = IntSinkNode(IntSinkPortSimple())