ethreg Test pass

2023-07-21 16:38:02 +08:00
parent 0b48e2cd2b
commit 21f8547273
3 changed files with 32 additions and 32 deletions
--- a/src/test/scala/gcd/Mac_test_top.scala
+++ b/src/test/scala/gcd/Mac_test_top.scala
@@ -37,9 +37,10 @@ class MacTest(implicit p: Parameters) extends Mac{
 			))
 		)))

-		val tlBar = TLXbar()
+	val tlBar = TLXbar()

-	tlMasterNode := tlBar := tlClientIONode
+	tlBar := tlClientIONode
+	tlMasterNode := tlBar
 	ethReg.configNode  := tlBar

 	val intSinkNode = IntSinkNode(IntSinkPortSimple())