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优化信号线命名negedge_sck

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Ruige Lee (WSL)
2025-10-01 08:41:43 +08:00
parent 8f564c0146
commit 21bc57e9a7
49 changed files with 21791 additions and 21789 deletions
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32
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -9,22 +9,24 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val io = IO(new RegAccessInterfaceIO)
val qspi = IO(new QSPIInterfaceIO)
val bitSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
val byteSel = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
val exRego = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val exRegi = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } }
val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val negedge_sck = (~qspi.sck).asClock
val spiLen = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiLenTemp = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiCnt = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
val isSpiWrite = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isSpiRead = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isPing_async = withClockAndReset((~qspi.sck).asClock, qspi.csn.asAsyncReset){ RegInit(false.B) }
val bitSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
val byteSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val exRegi = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } }
val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val spiLen = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiLenTemp = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiCnt = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
val isSpiWrite = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isSpiRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isPing_async = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }