优化信号线命名negedge_sck

src/main/scala/backBoard/shin/ShinTop.scala

@@ -1,64 +1,64 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-import chisel3.experimental.dataview._
-
-class ShinTopIO extends TopBase_IO_Bundle{
-  val multiCLK     = Input(Vec(16, Bool()))
-  val multiCLKDiv4 = Input(Vec(4, Bool()))
-}
-
-
-class ShinTop extends Module with RequireAsyncReset{
-  val io: ShinTopIO = IO(new ShinTopIO)
-
-  val mstSlvSwitch = Module(new MstSlvSwitch)
-
-
-
-  {
-    val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
-    val upCDRInSampleA   = Module(new CDRInMultiSample(clkNum = 16))
-
-    downCDRInSampleA.multiCLK := io.multiCLK
-    upCDRInSampleA.multiCLK   := io.multiCLK
-
-    downCDRInSampleA.io  <> mstSlvSwitch.io.downCDRSampleIn(0)
-    upCDRInSampleA.io    <> mstSlvSwitch.io.upCDRSampleIn(0)  
-  }
-
-  {
-    val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
-    val upCDRInSampleB   = Module(new CDRInMultiSample(clkNum = 4))
-
-    downCDRInSampleB.multiCLK := io.multiCLKDiv4
-    upCDRInSampleB.multiCLK   := io.multiCLKDiv4
-
-    downCDRInSampleB.io  <> mstSlvSwitch.io.downCDRSampleIn(1)
-    upCDRInSampleB.io    <> mstSlvSwitch.io.upCDRSampleIn(1)
-  }
-
-  {
-    val downCDRInSampleC = Module(new CDRInOriSample)
-    val upCDRInSampleC   = Module(new CDRInOriSample)
-
-    downCDRInSampleC.multiCLK := io.multiCLK
-    upCDRInSampleC.multiCLK   := io.multiCLK
-
-    downCDRInSampleC.io  <> mstSlvSwitch.io.downCDRSampleIn(2)
-    upCDRInSampleC.io    <> mstSlvSwitch.io.upCDRSampleIn(2)  
-  }
-
-
-
-  io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
-
-
-
-}
-
-
-
-
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+import chisel3.experimental.dataview._
+
+class ShinTopIO extends TopBase_IO_Bundle{
+  val multiCLK     = Input(Vec(16, Bool()))
+  val multiCLKDiv4 = Input(Vec(4, Bool()))
+}
+
+
+class ShinTop extends Module with RequireAsyncReset{
+  val io: ShinTopIO = IO(new ShinTopIO)
+
+  val mstSlvSwitch = Module(new MstSlvSwitch)
+
+
+
+  {
+    val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
+    val upCDRInSampleA   = Module(new CDRInMultiSample(clkNum = 16))
+
+    downCDRInSampleA.multiCLK := io.multiCLK
+    upCDRInSampleA.multiCLK   := io.multiCLK
+
+    downCDRInSampleA.io  <> mstSlvSwitch.io.downCDRSampleIn(0)
+    upCDRInSampleA.io    <> mstSlvSwitch.io.upCDRSampleIn(0)  
+  }
+
+  {
+    val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
+    val upCDRInSampleB   = Module(new CDRInMultiSample(clkNum = 4))
+
+    downCDRInSampleB.multiCLK := io.multiCLKDiv4
+    upCDRInSampleB.multiCLK   := io.multiCLKDiv4
+
+    downCDRInSampleB.io  <> mstSlvSwitch.io.downCDRSampleIn(1)
+    upCDRInSampleB.io    <> mstSlvSwitch.io.upCDRSampleIn(1)
+  }
+
+  {
+    val downCDRInSampleC = Module(new CDRInOriSample)
+    val upCDRInSampleC   = Module(new CDRInOriSample)
+
+    downCDRInSampleC.multiCLK := io.multiCLK
+    upCDRInSampleC.multiCLK   := io.multiCLK
+
+    downCDRInSampleC.io  <> mstSlvSwitch.io.downCDRSampleIn(2)
+    upCDRInSampleC.io    <> mstSlvSwitch.io.upCDRSampleIn(2)  
+  }
+
+
+
+  io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
+
+
+
+}
+
+
+
+