优化信号线命名negedge_sck
This commit is contained in:
Ruige Lee (WSL)
184
Makefile
184
Makefile
@@ -1,92 +1,92 @@
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TARGET=riscv64-unknown-elf
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RVCC=$(TARGET)-gcc
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RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
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ISR_MARCH=-march=rv32i -mabi=ilp32
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APP_MARCH=-march=rv32i -mabi=ilp32
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ISR_CFLAGS=-O2
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APP_CFLAGS=-O2
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SPI_TYPE ?= -spi 0
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TRANS_CODE ?=
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DEVCLK ?= --dev1 0 90 --dev2 0 -90
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CDRCLK ?= --clk 0 40
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CDR_TYPE ?= -cdr 0
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ifeq "$(RVCCVERSION)" "12.2.0"
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ISR_MARCH=-march=rv32izicsr -mabi=ilp32
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APP_MARCH=-march=rv32izicsr -mabi=ilp32
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endif
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.PHONY: compile tb wave
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shin:
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rm -f ./generated/shin/*
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rm -f ./generated/SimCDR/*
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sbt "test:runMain test.testShinModule"
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testShin:
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python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb.v
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vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
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python3 ./tb/shinTest/check_testcase.py
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testShinClk:
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python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest_clk.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb_clk.v
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vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
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python3 ./tb/shinTest/check_testcase.py
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testCDR:
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python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
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iverilog -Wall \
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-o ./tb/build/simCDR.iverilog \
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-y ./generated/SimCDR \
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-I ./generated/SimCDR \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/SimCDRTb.v
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vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
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testFilter:
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./tb/shinTest/test_filter.py
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vcdFilter:
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gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
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fstShin:
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gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
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fstShinClk:
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gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
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ef:
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sbt "test:runMain test.testModule"
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fst:
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gtkwave ./tb/build/wave.fst &
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debug_hlm:
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gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
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TARGET=riscv64-unknown-elf
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RVCC=$(TARGET)-gcc
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RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
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ISR_MARCH=-march=rv32i -mabi=ilp32
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APP_MARCH=-march=rv32i -mabi=ilp32
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ISR_CFLAGS=-O2
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APP_CFLAGS=-O2
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SPI_TYPE ?= -spi 0
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TRANS_CODE ?=
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DEVCLK ?= --dev1 0 90 --dev2 0 -90
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CDRCLK ?= --clk 0 40
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CDR_TYPE ?= -cdr 0
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ifeq "$(RVCCVERSION)" "12.2.0"
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ISR_MARCH=-march=rv32izicsr -mabi=ilp32
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APP_MARCH=-march=rv32izicsr -mabi=ilp32
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endif
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.PHONY: compile tb wave
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shin:
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rm -f ./generated/shin/*
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rm -f ./generated/SimCDR/*
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sbt "test:runMain test.testShinModule"
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testShin:
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python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb.v
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vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
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python3 ./tb/shinTest/check_testcase.py
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testShinClk:
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python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest_clk.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb_clk.v
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vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
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python3 ./tb/shinTest/check_testcase.py
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testCDR:
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python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
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iverilog -Wall \
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-o ./tb/build/simCDR.iverilog \
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-y ./generated/SimCDR \
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-I ./generated/SimCDR \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/SimCDRTb.v
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vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
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testFilter:
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./tb/shinTest/test_filter.py
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vcdFilter:
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gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
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fstShin:
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gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
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fstShinClk:
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gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
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ef:
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sbt "test:runMain test.testModule"
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fst:
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gtkwave ./tb/build/wave.fst &
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debug_hlm:
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gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
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