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测试改逻辑电路实现，明天重新调

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This commit is contained in:
Ruige Lee
2025-05-12 19:52:30 +08:00
parent afa1b9864f
commit 20b94fbe44
2 changed files with 310 additions and 182 deletions
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15
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -59,7 +59,7 @@ class SpiInterface extends Module{
val isSpiRead = spiCmd === 1.U val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W)) val bitSel = Reg(UInt(3.W))
val byteSel = Reg(UInt(5.W)) val byteSel = Reg(UInt(12.W))
// spiRegDown.io.addrr := Cat(pageSel, byteSel) // spiRegDown.io.addrr := Cat(pageSel, byteSel)
@@ -86,15 +86,16 @@ class SpiInterface extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U addrSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
when( byteSel === 0.U || byteSel === 1.U) { //CS为低，且SCK上跳的第0byte addrSel := exReg
addrSel := Cat( addrSel(14,0), shiftMOSI(1) ) } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U } .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel >= 3.U & bitSel === 0.U ){ when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){
addrSel := addrSel + 1.U addrSel := addrSel + 1.U
} }
} }
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U spiCmd := "hFF".U
@@ -113,7 +114,7 @@ class SpiInterface extends Module{
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exReg := io.datar exReg := io.datar
} .otherwise{ } .otherwise{
printf("Warning, empty CMD!\n") assert(false.B, "Assert Failed, empty CMD!\n")
} }
} }
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){

465
tb/shinTest/ShinTopSpiTb.v
View File

@@ -12,9 +12,9 @@ module ShinTopSpiTb(
wire [3:0] dDat_w; wire [3:0] dDat_w;
wire [3:0] uDat_w; wire [3:0] uDat_w;
reg [4:0] spi_sck; wire spi_sck;
reg [4:0] spi_mosi; wire spi_mosi;
wire [4:0] spi_miso; wire spi_miso;
reg [4:0] spi_csn; reg [4:0] spi_csn;
@@ -29,9 +29,9 @@ ShinTop s_ShinTop_Mst(
.io_uDatIn(uDat_w[0]), .io_uDatIn(uDat_w[0]),
.io_uDatOut(), .io_uDatOut(),
.io_ospi_sck (spi_sck[0]), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi[0]), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[0]), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[0]), .io_ospi_csn (spi_csn[0]),
.io_rsp_valid(), .io_rsp_valid(),
@@ -49,9 +49,9 @@ ShinTop s_ShinTop_slv0(
.io_uDatIn(uDat_w[1]), .io_uDatIn(uDat_w[1]),
.io_uDatOut(uDat_w[0]), .io_uDatOut(uDat_w[0]),
.io_ospi_sck (spi_sck[1]), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi[1]), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[1]), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[1]), .io_ospi_csn (spi_csn[1]),
.io_rsp_valid(), .io_rsp_valid(),
@@ -69,9 +69,9 @@ ShinTop s_ShinTop_slv1(
.io_uDatIn(uDat_w[2]), .io_uDatIn(uDat_w[2]),
.io_uDatOut(uDat_w[1]), .io_uDatOut(uDat_w[1]),
.io_ospi_sck (spi_sck[2]), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi[2]), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[2]), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[2]), .io_ospi_csn (spi_csn[2]),
.io_rsp_valid(), .io_rsp_valid(),
@@ -89,9 +89,9 @@ ShinTop s_ShinTop_slv2(
.io_uDatIn(uDat_w[3]), .io_uDatIn(uDat_w[3]),
.io_uDatOut(uDat_w[2]), .io_uDatOut(uDat_w[2]),
.io_ospi_sck (spi_sck[3]), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi[3]), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[3]), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[3]), .io_ospi_csn (spi_csn[3]),
.io_rsp_valid(), .io_rsp_valid(),
@@ -109,9 +109,9 @@ ShinTop s_ShinTop_slv3(
.io_uDatIn(1'b0), .io_uDatIn(1'b0),
.io_uDatOut(uDat_w[3]), .io_uDatOut(uDat_w[3]),
.io_ospi_sck (spi_sck[4]), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi[4]), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[4]), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[4]), .io_ospi_csn (spi_csn[4]),
.io_rsp_valid(), .io_rsp_valid(),
@@ -132,8 +132,6 @@ initial begin
clk8x = 0; clk8x = 0;
reset = 0; reset = 0;
spi_sck = 5'b0;
spi_mosi = 5'b0;
spi_csn = 5'b11111; spi_csn = 5'b11111;
#100 #100
@@ -142,7 +140,7 @@ initial begin
#240 #240
reset <= 0; reset <= 0;
#3000000 #10000000
$display("Time Out !!!"); $display("Time Out !!!");
$stop; $stop;
end end
@@ -183,68 +181,197 @@ end
`define SCKFRE #640
reg sck = 0;
initial begin initial begin
for( integer i = 0; i < 5; i = i + 1 ) begin
forever begin forever begin
#1000 spi_sck[i] <= spi_csn[i] == 1'b0 ? ~spi_sck[i] : 1'b0; `SCKFRE sck <= ~sck;
end
end end
end end
assign spi_sck = sck;
reg [7:0] txBuf[0:2047]; reg [7:0] txBuf[0:2047];
reg [7:0] rxBuf[0:2047]; reg [7:0] rxBuf[0:2047];
task spi_trans( input [15:0] address, input [7:0] cmd, input [10:0] length, input [7:0] idx );
reg [10:0] transCnt;
reg [7:0] exChangeReg; reg [7:0] exChangeReg;
reg [7:0] exChangeReg0;
reg [7:0] exChangeReg1;
reg [7:0] exChangeReg2;
reg [7:0] exChangeReg3;
reg [7:0] exChangeReg4;
// assign spi_mosi[0] = exChangeReg0[7];
// assign spi_mosi[1] = exChangeReg1[7];
// assign spi_mosi[2] = exChangeReg2[7];
// assign spi_mosi[3] = exChangeReg3[7];
// assign spi_mosi[4] = exChangeReg4[7];
assign spi_mosi = exChangeReg[7];
reg isReq = 0;
reg isBusy = 0;
reg [11:0] length;
reg [7:0] idx;
reg [11:0] transCnt;
reg [11:0] byteCnt;
reg [3:0] bitCnt;
always @(posedge sck) begin
if( isReq ) begin
isBusy <= #5 1'b1;
transCnt <= #5 0;
byteCnt <= #5 0;
bitCnt <= #5 0;
spi_csn[idx] <= #5 1'b0;
exChangeReg <= txBuf[0];
end
if( isBusy ) begin
if( transCnt < length ) begin
bitCnt <= bitCnt + 1;
if( bitCnt == 7 ) begin
byteCnt <= byteCnt +1;
rxBuf[byteCnt] <= exChangeReg;
exChangeReg <= txBuf[byteCnt+1];
end else begin
exChangeReg <= {exChangeReg[6:0], spi_miso};
end
end else begin
isBusy <= #5 1'b0;
spi_csn[idx] <= #5 1'b1;
end
end
end
// task spi_trans( );
// begin
// #10
// `SCKFRE spi_sck[idx] <= 1'b0;
// if( idx == 0 ) exChangeReg0 <= #5 address[7:0];
// else if( idx == 1 ) exChangeReg1 <= #5 address[7:0];
// else if( idx == 2 ) exChangeReg2 <= #5 address[7:0];
// else if( idx == 3 ) exChangeReg3 <= #5 address[7:0];
// else if( idx == 4 ) exChangeReg4 <= #5 address[7:0];
// `SCKFRE spi_sck[idx] <= 1'b1;
// `SCKFRE spi_sck[idx] <= 1'b0;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 address[15:8];
// else if( idx == 1 ) exChangeReg1 <= #5 address[15:8];
// else if( idx == 2 ) exChangeReg2 <= #5 address[15:8];
// else if( idx == 3 ) exChangeReg3 <= #5 address[15:8];
// else if( idx == 4 ) exChangeReg4 <= #5 address[15:8];
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 cmd;
// else if( idx == 1 ) exChangeReg1 <= #5 cmd;
// else if( idx == 2 ) exChangeReg2 <= #5 cmd;
// else if( idx == 3 ) exChangeReg3 <= #5 cmd;
// else if( idx == 4 ) exChangeReg4 <= #5 cmd;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// while( transCnt < length ) begin
// if( idx == 0 ) exChangeReg0 <= #5 txBuf[transCnt];
// else if( idx == 1 ) exChangeReg1 <= #5 txBuf[transCnt];
// else if( idx == 2 ) exChangeReg2 <= #5 txBuf[transCnt];
// else if( idx == 3 ) exChangeReg3 <= #5 txBuf[transCnt];
// else if( idx == 4 ) exChangeReg4 <= #5 txBuf[transCnt];
// transCnt <= transCnt + 1;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// rxBuf[transCnt] <= #5
// idx == 0 ? exChangeReg0 :
// idx == 1 ? exChangeReg1 :
// idx == 2 ? exChangeReg2 :
// idx == 3 ? exChangeReg3 :
// exChangeReg4;
// end
// spi_csn[idx] <= 1'b1;
// #2400
// spi_csn[idx] <= 1'b1;
// end
// endtask
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
begin begin
#10 txBuf[0] <= saddress[7:0];
spi_csn[idx] <= 1'b0; txBuf[1] <= saddress[15:8];
transCnt <= 0; txBuf[2] <= scmd;
exChangeReg <= address[7:0]; length <= slength;
repeat(8) begin idx <= sidx;
@(posedge spi_sck[idx]) #5
exChangeReg <= {exChangeReg[6:0], spi_miso[idx]}; #5
spi_mosi[idx] <= exChangeReg[7]; @(negedge sck)
end isReq <= 1;
exChangeReg <= address[15:8]; @(posedge sck) #5
repeat(8) begin isReq <= 0;
@(posedge spi_sck[idx]) #5
exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
spi_mosi[idx] <= exChangeReg[7];
end
exChangeReg <= cmd;
repeat(8) begin
@(posedge spi_sck[idx]) #5
exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
spi_mosi[idx] <= exChangeReg[7];
end
while( transCnt < length ) begin
exChangeReg <= txBuf[transCnt];
transCnt <= transCnt + 1;
repeat(8) begin
@(posedge spi_sck[idx]) #5
exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
spi_mosi[idx] <= exChangeReg[7];
end
rxBuf[transCnt] <= exChangeReg;
end end
@(negedge spi_sck[idx]) #5
spi_csn[idx] <= 1'b1;
end
endtask endtask
`define SPI_WRITE 8'h0 `define SPI_WRITE 8'h0
`define SPI_READ 8'h1 `define SPI_READ 8'h1
@@ -253,11 +380,11 @@ initial begin
#1000 #1000
//设置主站从站 //设置主站从站
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
spi_trans( (16'h0), (`SPI_WRITE), (1), (0) ); spi_trans( (16'h00), (`SPI_WRITE), (1), (0) );
#1000 #1000
txBuf[0] = 8'h02; txBuf[0+3] = 8'h02;
spi_trans( (16'h0), (`SPI_WRITE), (1), (1) ); spi_trans( (16'h0), (`SPI_WRITE), (1), (1) );
#1000 #1000
spi_trans( (16'h0), (`SPI_WRITE), (1), (2) ); spi_trans( (16'h0), (`SPI_WRITE), (1), (2) );
@@ -273,25 +400,25 @@ initial begin
begin begin
//设置SM1在写入0x3地址触发enq //设置SM1在写入0x3地址触发enq
txBuf[0] = 8'h03; txBuf[0+3] = 8'h03;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) ); spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
//无子报文 //无子报文
txBuf[0] = 8'h00; txBuf[0+3] = 8'h00;
txBuf[1] = 8'h01;//heeader length 0 嗅探包1 txBuf[1+3] = 8'h01;//heeader length 0 嗅探包1
txBuf[2] = 8'h00; txBuf[2+3] = 8'h00;
txBuf[3] = 8'h00; txBuf[3+3] = 8'h00;
spi_trans( (16'h1000), (`SPI_WRITE), (4), (0) ); //写入SM1 spi_trans( (16'h1000), (`SPI_WRITE), (4), (0) ); //写入SM1
//发布请求 //发布请求
txBuf[0] = 8'h04; txBuf[0+3] = 8'h04;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度 spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送 spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
end end
@@ -305,44 +432,44 @@ initial begin
#50000 #50000
#50000 #50000
#50000 #50000
$display("index @ %d", s_ShinTop_Mst.interface__io_timeStamp);
begin begin
//设置SM1在写入0xd地址触发enq //设置SM1在写入0xd地址触发enq
txBuf[0] = 8'h0d; txBuf[0+3] = 8'h0d;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) ); spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
txBuf[0] = 8'h00; txBuf[0+3] = 8'h00;
txBuf[1] = 8'ha0;//heeader length 10 txBuf[1+3] = 8'ha0;//heeader length 10
txBuf[2] = 8'h00; txBuf[2+3] = 8'h00;
txBuf[3] = 8'h00; txBuf[3+3] = 8'h00;
//子报文 //子报文
//设置顺序地址 //设置顺序地址
txBuf[4] = 8'h0; //设备索引 txBuf[4+3] = 8'h0; //设备索引
txBuf[5] = 8'h0; //设备索引、类型 txBuf[5+3] = 8'h0; //设备索引、类型
txBuf[6] = $random; //地址 txBuf[6+3] = $random; //地址
txBuf[7] = $random; //地址 txBuf[7+3] = $random; //地址
txBuf[8] = 8'hd0; //命令d 负载长度2 txBuf[8+3] = 8'hd0; //命令d 负载长度2
txBuf[9] = 8'd02; //负载长度2 txBuf[9+3] = 8'd02; //负载长度2
txBuf[10] = 8'h0; //工作计数0 txBuf[10+3] = 8'h0; //工作计数0
txBuf[11] = 8'h0; //工作计数0 txBuf[11+3] = 8'h0; //工作计数0
txBuf[12] = 8'h0; //负载 txBuf[12+3] = 8'h0; //负载
txBuf[13] = 8'h0; //负载 txBuf[13+3] = 8'h0; //负载
spi_trans( (16'h1000), (`SPI_WRITE), (14), (0) ); //写入SM1 spi_trans( (16'h1000), (`SPI_WRITE), (14), (0) ); //写入SM1
//发布请求 //发布请求
txBuf[0] = 8'h0e; txBuf[0+3] = 8'h0e;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度 spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送 spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
end end
@@ -353,88 +480,88 @@ initial begin
#50000 #50000
#50000 #50000
#50000 #50000
$display("read&write @ %d", s_ShinTop_Mst.interface__io_timeStamp);
begin begin
//设置SM1在写入516地址触发enq //设置SM1在写入516地址触发enq
txBuf[0] = 8'h03; txBuf[0+3] = 8'h03;
txBuf[1] = 8'h02; txBuf[1+3] = 8'h02;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) ); spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
txBuf[0] = 8'h20; txBuf[0+3] = 8'h20;
txBuf[1] = 8'h00;//heeader length 512 txBuf[1+3] = 8'h00;//heeader length 512
txBuf[2] = 8'h00; txBuf[2+3] = 8'h00;
txBuf[3] = 8'h00; txBuf[3+3] = 8'h00;
//子报文 //子报文
txBuf[4] = 8'h0; txBuf[4+3] = 8'h0;
txBuf[5] = 8'h8; //index = 2 txBuf[5+3] = 8'h8; //index = 2
txBuf[6] = 8'h08; //地址 //SM0 txBuf[6+3] = 8'h08; //地址 //SM0
txBuf[7] = 8'h30; //地址 //偏置 txBuf[7+3] = 8'h30; //地址 //偏置
txBuf[8] = 8'h20; //命令2 长度56 txBuf[8+3] = 8'h20; //命令2 长度56
txBuf[9] = 8'd56; //长度 txBuf[9+3] = 8'd56; //长度
txBuf[10] = $random; txBuf[10+3] = $random;
txBuf[11] = $random; txBuf[11+3] = $random;
for( integer j = 0; j < 64-8; j = j + 1 ) begin for( integer j = 0; j < 64-8; j = j + 1 ) begin
@(posedge clock) #3 @(posedge clock) #3
txBuf[12+j] = $random; txBuf[12+3+j] = $random;
end end
//------------------------- //-------------------------
//子报文 //子报文
txBuf[68] = 8'h0; txBuf[68+3] = 8'h0;
txBuf[69] = 8'h4; //index = 1 txBuf[69+3] = 8'h4; //index = 1
txBuf[70] = 8'h08; //地址 //SM0 txBuf[70+3] = 8'h08; //地址 //SM0
txBuf[71] = 8'h40; //地址 //偏置 txBuf[71+3] = 8'h40; //地址 //偏置
txBuf[72] = 8'h10; //命令1 长度56 txBuf[72+3] = 8'h10; //命令1 长度56
txBuf[73] = 8'd56; //长度 txBuf[73+3] = 8'd56; //长度
txBuf[74] = $random; txBuf[74+3] = $random;
txBuf[75] = $random; txBuf[75+3] = $random;
for( integer j = 0; j < 64-8; j = j + 1 ) begin for( integer j = 0; j < 64-8; j = j + 1 ) begin
@(posedge clock) #3 @(posedge clock) #3
txBuf[76+j] = $random; txBuf[76+3+j] = $random;
end end
//------------------------- //-------------------------
//子报文 //子报文
txBuf[132] = 8'h0; txBuf[132+3] = 8'h0;
txBuf[133] = 8'hc; //index = 3 txBuf[133+3] = 8'hc; //index = 3
txBuf[134] = 8'h09; //地址 //SM1 txBuf[134+3] = 8'h09; //地址 //SM1
txBuf[135] = 8'h40; //地址 //偏置 txBuf[135+3] = 8'h40; //地址 //偏置
txBuf[136] = 8'h00; //命令0 长度56 txBuf[136+3] = 8'h00; //命令0 长度56
txBuf[137] = 8'd56; //长度 txBuf[137+3] = 8'd56; //长度
txBuf[138] = $random; txBuf[138+3] = $random;
txBuf[139] = $random; txBuf[139+3] = $random;
for( integer j = 0; j < 64-8; j = j + 1 ) begin for( integer j = 0; j < 64-8; j = j + 1 ) begin
@(posedge clock) #3 @(posedge clock) #3
txBuf[140+j] = $random; txBuf[140+3+j] = $random;
end end
//------------------------- //-------------------------
for( integer i = 0 ; i < 5; i = i + 1) begin for( integer i = 0 ; i < 5; i = i + 1) begin
//子报文 //子报文
txBuf[196+i*64+0] = $random; txBuf[196+3+i*64+0] = $random;
txBuf[196+i*64+1] = 8'h0; //index = random txBuf[196+3+i*64+1] = 8'h0; //index = random
txBuf[196+i*64+2] = $random; txBuf[196+3+i*64+2] = $random;
txBuf[196+i*64+3] = $random; txBuf[196+3+i*64+3] = $random;
txBuf[196+i*64+4] = 8'h00; //命令0 长度56 txBuf[196+3+i*64+4] = 8'h00; //命令0 长度56
txBuf[196+i*64+5] = 8'd56; //长度 txBuf[196+3+i*64+5] = 8'd56; //长度
txBuf[196+i*64+6] = $random; txBuf[196+3+i*64+6] = $random;
txBuf[196+i*64+7] = $random; txBuf[196+3+i*64+7] = $random;
for( integer j = 0; j < 64-8; j = j + 1 ) begin for( integer j = 0; j < 64-8; j = j + 1 ) begin
@(posedge clock) #3 @(posedge clock) #3
txBuf[196+i*64+8+j] = $random; txBuf[196+3+i*64+8+j] = $random;
end end
end end
spi_trans( (16'h1000), (`SPI_WRITE), (516), (0) ); //写入SM1 spi_trans( (16'h1000), (`SPI_WRITE), (516), (0) ); //写入SM1
@@ -442,11 +569,11 @@ initial begin
//发布请求 //发布请求
txBuf[0] = 8'h04; txBuf[0+3] = 8'h04;
txBuf[1] = 8'h02; txBuf[1+3] = 8'h02;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度 spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送 spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
end end
@@ -469,55 +596,55 @@ initial begin
#90000 #90000
#90000 #90000
$display("sync @ %d", s_ShinTop_Mst.interface__io_timeStamp);
begin begin
//设置SM1在写入0x3地址触发enq //设置SM1在写入0x3地址触发enq
txBuf[0] = 8'h17; txBuf[0+3] = 8'h17;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) ); spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
txBuf[1] = 8'h40;//heeader length 20 txBuf[1+3] = 8'h40;//heeader length 20
txBuf[2] = 8'h00; txBuf[2+3] = 8'h00;
txBuf[3] = 8'h00; txBuf[3+3] = 8'h00;
//子报文 //子报文
//设置同步 //设置同步
txBuf[4] = 8'h0; //设备索引 txBuf[4+3] = 8'h0; //设备索引
txBuf[5] = 8'h0; //设备索引、类型 txBuf[5+3] = 8'h0; //设备索引、类型
txBuf[6] = $random; //地址 txBuf[6+3] = $random; //地址
txBuf[7] = $random; //地址 txBuf[7+3] = $random; //地址
txBuf[8] = 8'he0; //命令d 负载长度2 txBuf[8+3] = 8'he0; //命令d 负载长度2
txBuf[9] = 8'h0c; //负载长度c txBuf[9+3] = 8'h0c; //负载长度c
txBuf[10] = 8'h0; //工作计数0 txBuf[10+3] = 8'h0; //工作计数0
txBuf[11] = 8'h0; //工作计数0 txBuf[11+3] = 8'h0; //工作计数0
txBuf[12] = 0;//timeStamp[7:0]; //负载 txBuf[12+3] = 0;//timeStamp[7:0]; //负载
txBuf[13] = 0;//timeStamp[15:8]; //负载 txBuf[13+3] = 0;//timeStamp[15:8]; //负载
txBuf[14] = 0;//timeStamp[23:16]; //负载 txBuf[14+3] = 0;//timeStamp[23:16]; //负载
txBuf[15] = 0;//timeStamp[31:24]; //负载 txBuf[15+3] = 0;//timeStamp[31:24]; //负载
txBuf[16] = 0;//timeStamp[39:32]; //负载 txBuf[16+3] = 0;//timeStamp[39:32]; //负载
txBuf[17] = 0;//timeStamp[47:40]; //负载 txBuf[17+3] = 0;//timeStamp[47:40]; //负载
txBuf[18] = 0;//timeStamp[55:48]; //负载 txBuf[18+3] = 0;//timeStamp[55:48]; //负载
txBuf[19] = 0;//timeStamp[63:56]; //负载 txBuf[19+3] = 0;//timeStamp[63:56]; //负载
txBuf[20] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[ 7: 0]; //负载 txBuf[20+3] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[ 7: 0]; //负载
txBuf[21] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[15: 8]; //负载 txBuf[21+3] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[15: 8]; //负载
txBuf[22] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[23:16]; //负载 txBuf[22+3] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[23:16]; //负载
txBuf[23] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[31:24]; //负载 txBuf[23+3] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[31:24]; //负载
spi_trans( (16'h1000), (`SPI_WRITE), (24), (0) ); //写入SM1 spi_trans( (16'h1000), (`SPI_WRITE), (24), (0) ); //写入SM1
//发布请求 //发布请求
txBuf[0] = 8'h18; txBuf[0+3] = 8'h18;
txBuf[1] = 8'h00; txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度 spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0] = 8'h01; txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送 spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送