测试改逻辑电路实现，明天重新调

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -59,7 +59,7 @@ class SpiInterface extends Module{
   val isSpiRead  = spiCmd === 1.U
 
   val bitSel  = Reg(UInt(3.W))
-  val byteSel = Reg(UInt(5.W))
+  val byteSel = Reg(UInt(12.W))
 
 
 //   spiRegDown.io.addrr := Cat(pageSel, byteSel)
@@ -86,16 +86,17 @@ class SpiInterface extends Module{
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrSel := 0.U
-  } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
-    when( byteSel === 0.U || byteSel === 1.U) { //CS为低，且SCK上跳的第0byte
-      addrSel := Cat( addrSel(14,0), shiftMOSI(1) )
-    } .otherwise{ // byteSel > 1.U
-      when( isSckPosedgeNext(1) & byteSel >= 3.U & bitSel === 0.U ){
-        addrSel := addrSel + 1.U
-      }
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
+    addrSel := exReg
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
+    addrSel := Cat(exReg, addrSel(7,0))
+  } .otherwise{ // byteSel > 1.U
+    when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){
+      addrSel := addrSel + 1.U
     }
   }
 
+
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     spiCmd  := "hFF".U
   } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U ){ //CS为低，且SCK上跳的第0byte
@@ -113,7 +114,7 @@ class SpiInterface extends Module{
       } .elsewhen( isSpiRead ){
         exReg := io.datar
       } .otherwise{
-        printf("Warning, empty CMD!\n")
+        assert(false.B, "Assert Failed, empty CMD!\n")
       }
     }
   } .elsewhen( isSckPosedge & ~shiftCSn(1) ){