增加make testShin_vl的仿真选项,用以支持verilator的仿真;修改测试用例的数据

Makefile

@@ -24,6 +24,25 @@ shin:
 	rm -f ./generated/SimCDR/*
 	sbt "test:runMain test.testShinModule"
 
+testShin_vl:
+	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	rm -rf ./tb/build/
+	verilator -Wno-fatal  \
+	--timescale "1 ns / 1 ps" \
+	-y ./generated/shin \
+	--trace-fst \
+	--binary ./tb/shinTest/ShinTopSpiTb.v \
+	--top-module ShinTopSpiTb \
+	--Mdir ./tb/build/ \
+	+define+IVERILOG_COMPILE \
+	--threads 8 \
+	-j 0
+	./tb/build/VShinTopSpiTb
+	python3 ./tb/shinTest/check_testcase.py
+
+
 testShin:
 	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log