提供编译接口

Makefile

@@ -10,7 +10,13 @@ compile:
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
 # 	sbt "test:runMain test.testModule"
-	
+
+back:
+	sbt "test:runMain test.testModule"
+	cp ./src/main/verilog/backBoardMstTop.v ./generated/
+	cp ./src/main/verilog/backBoardSlvTop.v ./generated/
+	cp ./src/main/verilog/oser_rst.v ./generated/
+
 ef: 
 	sbt "test:runMain test.testModule"
 

src/test/scala/gcd/test.scala

@@ -13,13 +13,13 @@ import org.chipsalliance.cde.config._
 
 
 object testModule extends App {
-  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-  //     ChiselGeneratorAnnotation(() => { new BackBoardMst }),
+      ChiselGeneratorAnnotation(() => { new BackBoardMst }),
-  //   ))
+    ))
 
-  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-  //     ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
+      ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
-  //   ))
+    ))
 
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
   //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
@@ -35,16 +35,16 @@ object testModule extends App {
   // ))
 
 
-import Wrapeer._
+// import Wrapeer._
 
-  val cfg = new EfConfig
+//   val cfg = new EfConfig
 
-  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq(
+//   (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq(
-      ChiselGeneratorAnnotation(() => {
+//       ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new EfablessTop()(cfg))
+//     val soc = LazyModule(new EfablessTop()(cfg))
-    soc.module
+//     soc.module
-  })
+//   })
-  ))
+//   ))
 
 }