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提供编译接口

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This commit is contained in:
RuigeLee
2023-12-07 11:10:05 +08:00
parent 31213302aa
commit 1f898a7173
2 changed files with 21 additions and 15 deletions
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28
src/test/scala/gcd/test.scala
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@@ -13,13 +13,13 @@ import org.chipsalliance.cde.config._
object testModule extends App {
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardMst }),
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardMst }),
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
@@ -35,16 +35,16 @@ object testModule extends App {
// ))
import Wrapeer._
// import Wrapeer._
val cfg = new EfConfig
// val cfg = new EfConfig
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new EfablessTop()(cfg))
soc.module
})
))
// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main", "-E", "verilog") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new EfablessTop()(cfg))
// soc.module
// })
// ))
}