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提供编译接口

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RuigeLee
2023-12-07 11:10:05 +08:00
parent 31213302aa
commit 1f898a7173
2 changed files with 21 additions and 15 deletions
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8
Makefile
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@@ -10,7 +10,13 @@ compile:
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
# sbt "test:runMain test.testModule"
back:
sbt "test:runMain test.testModule"
cp ./src/main/verilog/backBoardMstTop.v ./generated/
cp ./src/main/verilog/backBoardSlvTop.v ./generated/
cp ./src/main/verilog/oser_rst.v ./generated/
ef:
sbt "test:runMain test.testModule"